arm64: dts: imx8ulp-evk: add spi-nor device support

Add spi-nor support.
- 8 bit mode for RX/TX.
- Set the clock rate to 200MHz.
- add default/sleep pinctrl.

Co-developed-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
index d66e31cf83fe63baaf168a9a37a47bf550c938da..f841b722597e571739ef05d4a2094d49b413a6ad 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
@@ -95,6 +95,21 @@
        status = "okay";
 };
 
+&flexspi2 {
+       pinctrl-names = "default", "sleep";
+       pinctrl-0 = <&pinctrl_flexspi2_ptd>;
+       pinctrl-1 = <&pinctrl_flexspi2_ptd>;
+       status = "okay";
+
+       mx25uw51345gxdi00: flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <200000000>;
+               spi-tx-bus-width = <8>;
+               spi-rx-bus-width = <8>;
+       };
+};
+
 &lpuart5 {
        /* console */
        pinctrl-names = "default", "sleep";
@@ -159,6 +174,23 @@
                >;
        };
 
+       pinctrl_flexspi2_ptd: flexspi2ptdgrp {
+               fsl,pins = <
+
+                       MX8ULP_PAD_PTD12__FLEXSPI2_A_SS0_B      0x42
+                       MX8ULP_PAD_PTD13__FLEXSPI2_A_SCLK       0x42
+                       MX8ULP_PAD_PTD14__FLEXSPI2_A_DATA3      0x42
+                       MX8ULP_PAD_PTD15__FLEXSPI2_A_DATA2      0x42
+                       MX8ULP_PAD_PTD16__FLEXSPI2_A_DATA1      0x42
+                       MX8ULP_PAD_PTD17__FLEXSPI2_A_DATA0      0x42
+                       MX8ULP_PAD_PTD18__FLEXSPI2_A_DQS        0x42
+                       MX8ULP_PAD_PTD19__FLEXSPI2_A_DATA7      0x42
+                       MX8ULP_PAD_PTD20__FLEXSPI2_A_DATA6      0x42
+                       MX8ULP_PAD_PTD21__FLEXSPI2_A_DATA5      0x42
+                       MX8ULP_PAD_PTD22__FLEXSPI2_A_DATA4      0x42
+               >;
+       };
+
        pinctrl_lpuart5: lpuart5grp {
                fsl,pins = <
                        MX8ULP_PAD_PTF14__LPUART5_TX    0x3