arm64: dts: qcom: ipq6018: enable the GICv2m support

GIC used in the IPQ6018 SoCs has one instance of the GICv2m extension,
which supports upto 32 MSI interrupts. Lets add support for the same.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1644334525-11577-3-git-send-email-quic_kathirav@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index aa8068193ccb3953ce8d588c7b99906a3438ffaf..f8b6d6263c61f70a36770b25eb7842dc77905ac9 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -373,6 +373,8 @@
 
                intc: interrupt-controller@b000000 {
                        compatible = "qcom,msm-qgic2";
+                       #address-cells = <2>;
+                       #size-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <0x3>;
                        reg =   <0x0 0x0b000000 0x0 0x1000>,  /*GICD*/
@@ -380,6 +382,13 @@
                                <0x0 0x0b001000 0x0 0x1000>,  /*GICH*/
                                <0x0 0x0b004000 0x0 0x1000>;  /*GICV*/
                        interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                       ranges = <0 0 0 0xb00a000 0 0xffd>;
+
+                       v2m@0 {
+                               compatible = "arm,gic-v2m-frame";
+                               msi-controller;
+                               reg = <0x0 0x0 0x0 0xffd>;
+                       };
                };
 
                pcie_phy: phy@84000 {