dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
authorEmil Renner Berthing <emil.renner.berthing@canonical.com>
Tue, 31 Oct 2023 14:14:43 +0000 (15:14 +0100)
committerConor Dooley <conor.dooley@microchip.com>
Wed, 22 Nov 2023 11:58:08 +0000 (11:58 +0000)
This cache controller is also used on the StarFive JH7100 SoC.
Unfortunately it needs a quirk to work properly, so add dedicated
compatible string to be able to match it.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Documentation/devicetree/bindings/cache/sifive,ccache0.yaml

index 8a6a78e1a7ab880dea6637ac40ed87289262ebbf..7e8cebe215846c11126f2dd9371660cb4e5c4594 100644 (file)
@@ -38,7 +38,9 @@ properties:
               - sifive,fu740-c000-ccache
           - const: cache
       - items:
-          - const: starfive,jh7110-ccache
+          - enum:
+              - starfive,jh7100-ccache
+              - starfive,jh7110-ccache
           - const: sifive,ccache0
           - const: cache
       - items:
@@ -88,6 +90,7 @@ allOf:
           contains:
             enum:
               - sifive,fu740-c000-ccache
+              - starfive,jh7100-ccache
               - starfive,jh7110-ccache
               - microchip,mpfs-ccache
 
@@ -111,6 +114,7 @@ allOf:
           contains:
             enum:
               - sifive,fu740-c000-ccache
+              - starfive,jh7100-ccache
               - starfive,jh7110-ccache
 
     then: