dt-bindings: mediatek: audsys: add support for MT8516
authorFabien Parent <fparent@baylibre.com>
Thu, 2 May 2019 12:18:42 +0000 (14:18 +0200)
committerStephen Boyd <sboyd@kernel.org>
Thu, 6 Jun 2019 22:56:09 +0000 (15:56 -0700)
Add AUDSYS device tree bindings documentation for MediaTek MT8516 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt
include/dt-bindings/clock/mt8516-clk.h

index f3cef1a6d95c7452ba534d6ab4851bbe080ab2e4..07c9d813465c9d2a5f14ddf06b1f09efe3d98621 100644 (file)
@@ -10,6 +10,7 @@ Required Properties:
        - "mediatek,mt7622-audsys", "syscon"
        - "mediatek,mt7623-audsys", "mediatek,mt2701-audsys", "syscon"
        - "mediatek,mt8183-audiosys", "syscon"
+       - "mediatek,mt8516-audsys", "syscon"
 - #clock-cells: Must be 1
 
 The AUDSYS controller uses the common clk binding from
index 9cfca53cd78d7b3862b89c99532c03f63f01987c..816447b98edd0bc2b25a96fee5838138592c28ae 100644 (file)
 #define CLK_TOP_MSDC2_INFRA            176
 #define CLK_TOP_NR_CLK                 177
 
+/* AUDSYS */
+
+#define CLK_AUD_AFE                    0
+#define CLK_AUD_I2S                    1
+#define CLK_AUD_22M                    2
+#define CLK_AUD_24M                    3
+#define CLK_AUD_INTDIR                 4
+#define CLK_AUD_APLL2_TUNER            5
+#define CLK_AUD_APLL_TUNER             6
+#define CLK_AUD_HDMI                   7
+#define CLK_AUD_SPDF                   8
+#define CLK_AUD_ADC                    9
+#define CLK_AUD_DAC                    10
+#define CLK_AUD_DAC_PREDIS             11
+#define CLK_AUD_TML                    12
+#define CLK_AUD_NR_CLK                 13
+
 #endif /* _DT_BINDINGS_CLK_MT8516_H */