iio: adc: meson-saradc: remove #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT

This define is of no use because the driver is avoiding shifting bits
by itself but using FIELD_GET/FIELD_PREP (which are using bit masks)
instead. There is already a MESON_SAR_ADC_DELTA_10_TS_C_MASK bit mask so
MESON_SAR_ADC_DELTA_10_TS_C_SHIFT was redundant.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index da2d16dfa63e3b4eacaca90d8e07c521a85284ea..b97b06bf77137f3038da7f26c8c4975545771df4 100644 (file)
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -148,7 +148,6 @@
        #define MESON_SAR_ADC_DELTA_10_TS_REVE1                 BIT(26)
        #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK   GENMASK(25, 16)
        #define MESON_SAR_ADC_DELTA_10_TS_REVE0                 BIT(15)
-       #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT               11
        #define MESON_SAR_ADC_DELTA_10_TS_C_MASK                GENMASK(14, 11)
        #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN                BIT(10)
        #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK   GENMASK(9, 0)