net/mlx5: Add structure and defines for pci sync for fw update event

Add needed structure layouts and defines for pci sync for fw update
event. The downstream patches will include event handlers for this event
type.

Signed-off-by: Moshe Shemesh <moshe@mellanox.com>
Reviewed-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 746e17473d721e9885c8aea9a350e9d7e801237a..de93f0b679737e85ca57b415b1382696a0323b57 100644 (file)
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -364,6 +364,7 @@ enum {
 enum {
        MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
        MLX5_GENERAL_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
+       MLX5_GENERAL_SUBTYPE_PCI_SYNC_FOR_FW_UPDATE_EVENT = 0x8,
 };
 
 enum {
@@ -689,6 +690,19 @@ struct mlx5_eqe_temp_warning {
        __be64 sensor_warning_lsb;
 } __packed;
 
+#define SYNC_RST_STATE_MASK    0xf
+
+enum sync_rst_state_type {
+       MLX5_SYNC_RST_STATE_RESET_REQUEST       = 0x0,
+       MLX5_SYNC_RST_STATE_RESET_NOW           = 0x1,
+       MLX5_SYNC_RST_STATE_RESET_ABORT         = 0x2,
+};
+
+struct mlx5_eqe_sync_fw_update {
+       u8 reserved_at_0[3];
+       u8 sync_rst_state;
+};
+
 union ev_data {
        __be32                          raw[7];
        struct mlx5_eqe_cmd             cmd;
@@ -707,6 +721,7 @@ union ev_data {
        struct mlx5_eqe_dct             dct;
        struct mlx5_eqe_temp_warning    temp_warning;
        struct mlx5_eqe_xrq_err         xrq_err;
+       struct mlx5_eqe_sync_fw_update  sync_fw_update;
 } __packed;
 
 struct mlx5_eqe {

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 9e6a3cec1e32f830e8c0be22a0dbf97abbc60426..058ded202b6501221bca34df02bade9e53fc6c14 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1317,7 +1317,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
        u8         wol_p[0x1];
 
        u8         stat_rate_support[0x10];
-       u8         reserved_at_1f0[0xc];
+       u8         reserved_at_1f0[0x1];
+       u8         pci_sync_for_fw_update_event[0x1];
+       u8         reserved_at_1f2[0xa];
        u8         cqe_version[0x4];
 
        u8         compact_address_vector[0x1];