drm/amd/display: Disable OTG for mode timing switch on DCN35
authorOvidiu Bunea <ovidiu.bunea@amd.com>
Wed, 25 Oct 2023 17:05:47 +0000 (13:05 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 7 Nov 2023 17:03:30 +0000 (12:03 -0500)
[why]
Doing a mode timing change causes a hang when OTG is not disabled.

[how]
Add link_enc null check in disable_otg_wa to cover this case.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c

index 085ac191c94fcaff18f0a10f15718344cf070c89..0fa4fcd00de2c982ebc2634c7a74f19585c3b721 100644 (file)
@@ -124,7 +124,8 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *
 
                if (pipe->top_pipe || pipe->prev_odm_pipe)
                        continue;
-               if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
+               if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) ||
+                                    !pipe->stream->link_enc)) {
                        struct stream_encoder *stream_enc = pipe->stream_res.stream_enc;
 
                        if (disable) {