ARM: dts: dra74x: convert IOMMUs to use ti-sysc

Convert dra74x IOMMUs to use ti-sysc instead of legacy omap-hwmod based
implementation. Enable the IOMMUs also while doing this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index d1b5b76bc5a82896e064d60853d5f67e0865481c..c5abc436ca1f5c171e2bbc17a3b97e2e9a296bf3 100644 (file)
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -66,24 +66,63 @@
                        };
                };
 
-               mmu0_dsp2: mmu@41501000 {
-                       compatible = "ti,dra7-dsp-iommu";
-                       reg = <0x41501000 0x100>;
-                       interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "mmu0_dsp2";
-                       #iommu-cells = <0>;
-                       ti,syscon-mmuconfig = <&dsp2_system 0x0>;
-                       status = "disabled";
+               target-module@41501000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       reg = <0x41501000 0x4>,
+                             <0x41501010 0x4>,
+                             <0x41501014 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+                       clock-names = "fck";
+                       resets = <&prm_dsp2 1>;
+                       reset-names = "rstctrl";
+                       ranges = <0x0 0x41501000 0x1000>;
+                       #size-cells = <1>;
+                       #address-cells = <1>;
+
+                       mmu0_dsp2: mmu@0 {
+                               compatible = "ti,dra7-dsp-iommu";
+                               reg = <0x0 0x100>;
+                               interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+                               #iommu-cells = <0>;
+                               ti,syscon-mmuconfig = <&dsp2_system 0x0>;
+                       };
                };
 
-               mmu1_dsp2: mmu@41502000 {
-                       compatible = "ti,dra7-dsp-iommu";
-                       reg = <0x41502000 0x100>;
-                       interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
-                       ti,hwmods = "mmu1_dsp2";
-                       #iommu-cells = <0>;
-                       ti,syscon-mmuconfig = <&dsp2_system 0x1>;
-                       status = "disabled";
+               target-module@41502000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
+                       reg = <0x41502000 0x4>,
+                             <0x41502010 0x4>,
+                             <0x41502014 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>;
+                       ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+                                        SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+
+                       clocks = <&dsp2_clkctrl DRA7_DSP2_MMU0_DSP2_CLKCTRL 0>;
+                       clock-names = "fck";
+                       resets = <&prm_dsp2 1>;
+                       reset-names = "rstctrl";
+                       ranges = <0x0 0x41502000 0x1000>;
+                       #size-cells = <1>;
+                       #address-cells = <1>;
+
+                       mmu1_dsp2: mmu@0 {
+                               compatible = "ti,dra7-dsp-iommu";
+                               reg = <0x0 0x100>;
+                               interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+                               #iommu-cells = <0>;
+                               ti,syscon-mmuconfig = <&dsp2_system 0x1>;
+                       };
                };
        };
 };