riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node

Add PLL clocks input from PLL clocks driver in SYSCRG node.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 0cfa66e7196321ae5efd6ff0b483dbf24d68eaf8..7f02b8b8287d00bd6e21759f11efa8e5bf280c78 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -517,12 +517,16 @@
                                 <&gmac1_rgmii_rxin>,
                                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-                                <&tdm_ext>, <&mclk_ext>;
+                                <&tdm_ext>, <&mclk_ext>,
+                                <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+                                <&pllclk JH7110_PLLCLK_PLL1_OUT>,
+                                <&pllclk JH7110_PLLCLK_PLL2_OUT>;
                        clock-names = "osc", "gmac1_rmii_refin",
                                      "gmac1_rgmii_rxin",
                                      "i2stx_bclk_ext", "i2stx_lrck_ext",
                                      "i2srx_bclk_ext", "i2srx_lrck_ext",
-                                     "tdm_ext", "mclk_ext";
+                                     "tdm_ext", "mclk_ext",
+                                     "pll0_out", "pll1_out", "pll2_out";
                        #clock-cells = <1>;
                        #reset-cells = <1>;
                };