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arm64: dts: rockchip: Add sfc node to rk3588s
author
Muhammed Efe Cetin
<efectn@6tel.net>
Mon, 9 Oct 2023 19:27:26 +0000
(22:27 +0300)
committer
Heiko Stuebner
<heiko@sntech.de>
Mon, 9 Oct 2023 23:35:26 +0000
(
01:35
+0200)
Add SFC (SPI Flash) to RK3588S SOC.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net>
Link:
https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
patch
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blob
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diff --git
a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
index 5544f66c6ff411af3a3ccc9071682ace80410977..1a820a5a51eb0ae532734a16fefd013062a40ed1 100644
(file)
--- a/
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+++ b/
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
@@
-1424,6
+1424,17
@@
};
};
+ sfc: spi@fe2b0000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe2b0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
sdmmc: mmc@fe2c0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x0 0xfe2c0000 0x0 0x4000>;