fault_info->status);
        }
 
+       drm_printf(&p, "Ring buffer information\n");
+       for (int i = 0; i < coredump->adev->num_rings; i++) {
+               int j = 0;
+               struct amdgpu_ring *ring = coredump->adev->rings[i];
+
+               drm_printf(&p, "ring name: %s\n", ring->name);
+               drm_printf(&p, "Rptr: 0x%llx Wptr: 0x%llx RB mask: %x\n",
+                          amdgpu_ring_get_rptr(ring),
+                          amdgpu_ring_get_wptr(ring),
+                          ring->buf_mask);
+               drm_printf(&p, "Ring size in dwords: %d\n",
+                          ring->ring_size / 4);
+               drm_printf(&p, "Ring contents\n");
+               drm_printf(&p, "Offset \t Value\n");
+
+               while (j < ring->ring_size) {
+                       drm_printf(&p, "0x%x \t 0x%x\n", j, ring->ring[j/4]);
+                       j += 4;
+               }
+       }
+
        if (coredump->reset_vram_lost)
                drm_printf(&p, "VRAM is lost due to GPU reset!\n");
        if (coredump->adev->reset_info.num_regs) {