ARM: dts: at91: use clock-controller name for sckc nodes
authorClaudiu Beznea <claudiu.beznea@microchip.com>
Wed, 17 May 2023 09:41:18 +0000 (12:41 +0300)
committerClaudiu Beznea <claudiu.beznea@microchip.com>
Mon, 22 May 2023 13:00:34 +0000 (16:00 +0300)
Use clock-controller generic name for slow clock controller nodes.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20230517094119.2894220-5-claudiu.beznea@microchip.com
arch/arm/boot/dts/at91sam9g45.dtsi
arch/arm/boot/dts/at91sam9rl.dtsi
arch/arm/boot/dts/at91sam9x5.dtsi
arch/arm/boot/dts/sam9x60.dtsi
arch/arm/boot/dts/sama5d2.dtsi
arch/arm/boot/dts/sama5d3.dtsi
arch/arm/boot/dts/sama5d4.dtsi

index 76afeb31b7f54ef5a5bf4733816bec11756d604a..498cb92b29f96a5fff17a29e87853ea36b010cc1 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fffffd50 {
+                       clk32k: clock-controller@fffffd50 {
                                compatible = "atmel,at91sam9x5-sckc";
                                reg = <0xfffffd50 0x4>;
                                clocks = <&slow_xtal>;
index a12e6c419fe3dbc476c7248e77aa62f01715c18f..d7e8a115c916c5613c0697196fde71e82c144f8f 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fffffd50 {
+                       clk32k: clock-controller@fffffd50 {
                                compatible = "atmel,at91sam9x5-sckc";
                                reg = <0xfffffd50 0x4>;
                                clocks = <&slow_xtal>;
index af19ef2a875c49f92d2336569a504c3945ec3f1f..0123ee47151cb7b4ea880bc41e02f7f74bd6964f 100644 (file)
                                clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
                        };
 
-                       clk32k: sckc@fffffe50 {
+                       clk32k: clock-controller@fffffe50 {
                                compatible = "atmel,at91sam9x5-sckc";
                                reg = <0xfffffe50 0x4>;
                                clocks = <&slow_xtal>;
index 89aafb9a8b0fe7f0dc31955813b1e9002965ed56..c8bedfa987e572dbc626286a7b3c10751b1edda7 100644 (file)
                                clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
                        };
 
-                       clk32k: sckc@fffffe50 {
+                       clk32k: clock-controller@fffffe50 {
                                compatible = "microchip,sam9x60-sckc";
                                reg = <0xfffffe50 0x4>;
                                clocks = <&slow_xtal>;
index 86009dd28e623f5ac650e6d457f983af08df392c..5f632e3f039e6016571ce3b32c317f76c6e85436 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@f8048050 {
+                       clk32k: clock-controller@f8048050 {
                                compatible = "atmel,sama5d4-sckc";
                                reg = <0xf8048050 0x4>;
 
index 4524a16322d16b4ceadbf92390c47e249c26fafd..0eebf6c760b3d30deb3281894ccddea6225f17d6 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fffffe50 {
+                       clk32k: clock-controller@fffffe50 {
                                compatible = "atmel,sama5d3-sckc";
                                reg = <0xfffffe50 0x4>;
                                clocks = <&slow_xtal>;
index e94f3a661f4bb0eefe74a7fe51e5e7d69c59a133..de6c829692327ce8e9d0a33eea090fe8ef5aa78d 100644 (file)
                                status = "disabled";
                        };
 
-                       clk32k: sckc@fc068650 {
+                       clk32k: clock-controller@fc068650 {
                                compatible = "atmel,sama5d4-sckc";
                                reg = <0xfc068650 0x4>;
                                #clock-cells = <0>;