clk: vc5: Use `clamp()` to restrict PLL range

The VCO frequency needs to be within a certain range and the driver
enforces this.

Make use of the clamp macro to implement this instead of open-coding it.
This makes the code a bit shorter and also semanticly stronger.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Link: https://lore.kernel.org/r/20230114233500.3294789-1-lars@metafoo.de
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index e9737969170e1e08548f8bcdc084eaf1c6f675c9..54fee43d65642f4b04876d751b9b3213cb2e0897 100644 (file)
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -449,10 +449,7 @@ static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
        u32 div_int;
        u64 div_frc;
 
-       if (rate < VC5_PLL_VCO_MIN)
-               rate = VC5_PLL_VCO_MIN;
-       if (rate > VC5_PLL_VCO_MAX)
-               rate = VC5_PLL_VCO_MAX;
+       rate = clamp(rate, VC5_PLL_VCO_MIN, VC5_PLL_VCO_MAX);
 
        /* Determine integer part, which is 12 bit wide */
        div_int = rate / *parent_rate;