arm64: dts: mediatek: mt7986: reorder nodes

Use order described as preferred in DTS Coding Style:
1. Sort bus nodes by unit address
2. Use alpha-numerical order for the rest

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Link: https://lore.kernel.org/r/20240212121620.15035-2-zajec5@gmail.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
index eba5e27a1bbead74e6994a591f729d82d35796d5..b3f416b9a7a4da6c15c040c160ee6d6203979aeb 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -16,13 +16,6 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
-       clk40m: oscillator-40m {
-               compatible = "fixed-clock";
-               clock-frequency = <40000000>;
-               #clock-cells = <0>;
-               clock-output-names = "clkxtal";
-       };
-
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -59,6 +52,13 @@
                };
        };
 
+       clk40m: oscillator-40m {
+               compatible = "fixed-clock";
+               clock-frequency = <40000000>;
+               #clock-cells = <0>;
+               clock-output-names = "clkxtal";
+       };
+
        psci {
                compatible = "arm,psci-0.2";
                method = "smc";
@@ -121,15 +121,6 @@
 
        };
 
-       timer {
-               compatible = "arm,armv8-timer";
-               interrupt-parent = <&gic>;
-               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
-                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
-       };
-
        soc {
                compatible = "simple-bus";
                ranges;
@@ -203,6 +194,19 @@
                        #interrupt-cells = <2>;
                };
 
+               pwm: pwm@10048000 {
+                       compatible = "mediatek,mt7986-pwm";
+                       reg = <0 0x10048000 0 0x1000>;
+                       #pwm-cells = <2>;
+                       interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&topckgen CLK_TOP_PWM_SEL>,
+                                <&infracfg CLK_INFRA_PWM_STA>,
+                                <&infracfg CLK_INFRA_PWM1_CK>,
+                                <&infracfg CLK_INFRA_PWM2_CK>;
+                       clock-names = "top", "main", "pwm1", "pwm2";
+                       status = "disabled";
+               };
+
                sgmiisys0: syscon@10060000 {
                        compatible = "mediatek,mt7986-sgmiisys_0",
                                     "syscon";
@@ -240,19 +244,6 @@
                        status = "disabled";
                };
 
-               pwm: pwm@10048000 {
-                       compatible = "mediatek,mt7986-pwm";
-                       reg = <0 0x10048000 0 0x1000>;
-                       #pwm-cells = <2>;
-                       interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&topckgen CLK_TOP_PWM_SEL>,
-                                <&infracfg CLK_INFRA_PWM_STA>,
-                                <&infracfg CLK_INFRA_PWM1_CK>,
-                                <&infracfg CLK_INFRA_PWM2_CK>;
-                       clock-names = "top", "main", "pwm1", "pwm2";
-                       status = "disabled";
-               };
-
                uart0: serial@11002000 {
                        compatible = "mediatek,mt7986-uart",
                                     "mediatek,mt6577-uart";
@@ -336,6 +327,21 @@
                        status = "disabled";
                };
 
+               thermal: thermal@1100c800 {
+                       compatible = "mediatek,mt7986-thermal";
+                       reg = <0 0x1100c800 0 0x800>;
+                       interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&infracfg CLK_INFRA_THERM_CK>,
+                                <&infracfg CLK_INFRA_ADC_26M_CK>,
+                                <&infracfg CLK_INFRA_ADC_FRC_CK>;
+                       clock-names = "therm", "auxadc", "adc_32k";
+                       nvmem-cells = <&thermal_calibration>;
+                       nvmem-cell-names = "calibration-data";
+                       #thermal-sensor-cells = <1>;
+                       mediatek,auxadc = <&auxadc>;
+                       mediatek,apmixedsys = <&apmixedsys>;
+               };
+
                auxadc: adc@1100d000 {
                        compatible = "mediatek,mt7986-auxadc";
                        reg = <0 0x1100d000 0 0x1000>;
@@ -387,21 +393,6 @@
                        status = "disabled";
                };
 
-               thermal: thermal@1100c800 {
-                       compatible = "mediatek,mt7986-thermal";
-                       reg = <0 0x1100c800 0 0x800>;
-                       interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&infracfg CLK_INFRA_THERM_CK>,
-                                <&infracfg CLK_INFRA_ADC_26M_CK>,
-                                <&infracfg CLK_INFRA_ADC_FRC_CK>;
-                       clock-names = "therm", "auxadc", "adc_32k";
-                       nvmem-cells = <&thermal_calibration>;
-                       nvmem-cell-names = "calibration-data";
-                       #thermal-sensor-cells = <1>;
-                       mediatek,auxadc = <&auxadc>;
-                       mediatek,apmixedsys = <&apmixedsys>;
-               };
-
                pcie: pcie@11280000 {
                        compatible = "mediatek,mt7986-pcie",
                                     "mediatek,mt8192-pcie";
@@ -533,20 +524,6 @@
                        mediatek,wo-ccif = <&wo_ccif1>;
                };
 
-               wo_ccif0: syscon@151a5000 {
-                       compatible = "mediatek,mt7986-wo-ccif", "syscon";
-                       reg = <0 0x151a5000 0 0x1000>;
-                       interrupt-parent = <&gic>;
-                       interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
-               };
-
-               wo_ccif1: syscon@151ad000 {
-                       compatible = "mediatek,mt7986-wo-ccif", "syscon";
-                       reg = <0 0x151ad000 0 0x1000>;
-                       interrupt-parent = <&gic>;
-                       interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
-               };
-
                eth: ethernet@15100000 {
                        compatible = "mediatek,mt7986-eth";
                        reg = <0 0x15100000 0 0x80000>;
@@ -589,6 +566,20 @@
                        status = "disabled";
                };
 
+               wo_ccif0: syscon@151a5000 {
+                       compatible = "mediatek,mt7986-wo-ccif", "syscon";
+                       reg = <0 0x151a5000 0 0x1000>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               wo_ccif1: syscon@151ad000 {
+                       compatible = "mediatek,mt7986-wo-ccif", "syscon";
+                       reg = <0 0x151ad000 0 0x1000>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
                wifi: wifi@18000000 {
                        compatible = "mediatek,mt7986-wmac";
                        reg = <0 0x18000000 0 0x1000000>,
@@ -646,4 +637,13 @@
                        };
                };
        };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+       };
 };