crypto: qat - expand CSR operations for QAT GEN4 devices

Extend the CSR operations for QAT GEN4 devices to allow saving and
restoring the rings state.

The new operations will be used as a building block for implementing the
state save and restore of Virtual Functions necessary for VM live
migration.

This adds the following operations:
 - read ring status register
 - read ring underflow/overflow status register
 - read ring nearly empty status register
 - read ring nearly full status register
 - read ring full status register
 - read ring complete status register
 - read ring exception status register
 - read/write ring exception interrupt mask register
 - read ring configuration register
 - read ring base register
 - read/write ring interrupt enable register
 - read ring interrupt flag register
 - read/write ring interrupt source select register
 - read ring coalesced interrupt enable register
 - read ring coalesced interrupt control register
 - read ring flag and coalesced interrupt enable register
 - read ring service arbiter enable register
 - get ring coalesced interrupt control enable mask

Signed-off-by: Siming Wan <siming.wan@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Xin Zeng <xin.zeng@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

diff --git a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
index 08658c3a01e9bcde41ecef655fbdab0e8291ac99..d1f3f5a822fff4116b20eb9e6b4fbf216a34bc81 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
@@ -150,22 +150,49 @@ struct adf_hw_csr_ops {
                                  u32 ring);
        void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
                                    u32 ring, u32 value);
+       u32 (*read_csr_stat)(void __iomem *csr_base_addr, u32 bank);
+       u32 (*read_csr_uo_stat)(void __iomem *csr_base_addr, u32 bank);
        u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
+       u32 (*read_csr_ne_stat)(void __iomem *csr_base_addr, u32 bank);
+       u32 (*read_csr_nf_stat)(void __iomem *csr_base_addr, u32 bank);
+       u32 (*read_csr_f_stat)(void __iomem *csr_base_addr, u32 bank);
+       u32 (*read_csr_c_stat)(void __iomem *csr_base_addr, u32 bank);
+       u32 (*read_csr_exp_stat)(void __iomem *csr_base_addr, u32 bank);
+       u32 (*read_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank);
+       void (*write_csr_exp_int_en)(void __iomem *csr_base_addr, u32 bank,
+                                    u32 value);
+       u32 (*read_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
+                                   u32 ring);
        void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
                                      u32 ring, u32 value);
+       dma_addr_t (*read_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
+                                        u32 ring);
        void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
                                    u32 ring, dma_addr_t addr);
+       u32 (*read_csr_int_en)(void __iomem *csr_base_addr, u32 bank);
+       void (*write_csr_int_en)(void __iomem *csr_base_addr, u32 bank,
+                                u32 value);
+       u32 (*read_csr_int_flag)(void __iomem *csr_base_addr, u32 bank);
        void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
                                   u32 value);
+       u32 (*read_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
        void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
+       void (*write_csr_int_srcsel_w_val)(void __iomem *csr_base_addr,
+                                          u32 bank, u32 value);
+       u32 (*read_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank);
        void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
                                     u32 value);
+       u32 (*read_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank);
        void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
                                      u32 value);
+       u32 (*read_csr_int_flag_and_col)(void __iomem *csr_base_addr,
+                                        u32 bank);
        void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
                                           u32 bank, u32 value);
+       u32 (*read_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank);
        void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
                                          u32 value);
+       u32 (*get_int_col_ctl_enable_mask)(void);
 };
 
 struct adf_cfg_device_data;

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c
index 652ef4598930360ef0a795120cd669888a23c50e..6609c248aaba5da8683ad4900163d5642d03c272 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.c
@@ -30,57 +30,166 @@ static void write_csr_ring_tail(void __iomem *csr_base_addr, u32 bank, u32 ring,
        WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value);
 }
 
+static u32 read_csr_stat(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_STAT(csr_base_addr, bank);
+}
+
+static u32 read_csr_uo_stat(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_UO_STAT(csr_base_addr, bank);
+}
+
 static u32 read_csr_e_stat(void __iomem *csr_base_addr, u32 bank)
 {
        return READ_CSR_E_STAT(csr_base_addr, bank);
 }
 
+static u32 read_csr_ne_stat(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_NE_STAT(csr_base_addr, bank);
+}
+
+static u32 read_csr_nf_stat(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_NF_STAT(csr_base_addr, bank);
+}
+
+static u32 read_csr_f_stat(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_F_STAT(csr_base_addr, bank);
+}
+
+static u32 read_csr_c_stat(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_C_STAT(csr_base_addr, bank);
+}
+
+static u32 read_csr_exp_stat(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_EXP_STAT(csr_base_addr, bank);
+}
+
+static u32 read_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_EXP_INT_EN(csr_base_addr, bank);
+}
+
+static void write_csr_exp_int_en(void __iomem *csr_base_addr, u32 bank,
+                                u32 value)
+{
+       WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value);
+}
+
+static u32 read_csr_ring_config(void __iomem *csr_base_addr, u32 bank,
+                               u32 ring)
+{
+       return READ_CSR_RING_CONFIG(csr_base_addr, bank, ring);
+}
+
 static void write_csr_ring_config(void __iomem *csr_base_addr, u32 bank, u32 ring,
                                  u32 value)
 {
        WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value);
 }
 
+static dma_addr_t read_csr_ring_base(void __iomem *csr_base_addr, u32 bank,
+                                    u32 ring)
+{
+       return READ_CSR_RING_BASE(csr_base_addr, bank, ring);
+}
+
 static void write_csr_ring_base(void __iomem *csr_base_addr, u32 bank, u32 ring,
                                dma_addr_t addr)
 {
        WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, addr);
 }
 
+static u32 read_csr_int_en(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_INT_EN(csr_base_addr, bank);
+}
+
+static void write_csr_int_en(void __iomem *csr_base_addr, u32 bank, u32 value)
+{
+       WRITE_CSR_INT_EN(csr_base_addr, bank, value);
+}
+
+static u32 read_csr_int_flag(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_INT_FLAG(csr_base_addr, bank);
+}
+
 static void write_csr_int_flag(void __iomem *csr_base_addr, u32 bank,
                               u32 value)
 {
        WRITE_CSR_INT_FLAG(csr_base_addr, bank, value);
 }
 
+static u32 read_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_INT_SRCSEL(csr_base_addr, bank);
+}
+
 static void write_csr_int_srcsel(void __iomem *csr_base_addr, u32 bank)
 {
        WRITE_CSR_INT_SRCSEL(csr_base_addr, bank);
 }
 
+static void write_csr_int_srcsel_w_val(void __iomem *csr_base_addr, u32 bank,
+                                      u32 value)
+{
+       WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr, bank, value);
+}
+
+static u32 read_csr_int_col_en(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_INT_COL_EN(csr_base_addr, bank);
+}
+
 static void write_csr_int_col_en(void __iomem *csr_base_addr, u32 bank, u32 value)
 {
        WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value);
 }
 
+static u32 read_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_INT_COL_CTL(csr_base_addr, bank);
+}
+
 static void write_csr_int_col_ctl(void __iomem *csr_base_addr, u32 bank,
                                  u32 value)
 {
        WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value);
 }
 
+static u32 read_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_INT_FLAG_AND_COL(csr_base_addr, bank);
+}
+
 static void write_csr_int_flag_and_col(void __iomem *csr_base_addr, u32 bank,
                                       u32 value)
 {
        WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value);
 }
 
+static u32 read_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank)
+{
+       return READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank);
+}
+
 static void write_csr_ring_srv_arb_en(void __iomem *csr_base_addr, u32 bank,
                                      u32 value)
 {
        WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value);
 }
 
+static u32 get_int_col_ctl_enable_mask(void)
+{
+       return ADF_RING_CSR_INT_COL_CTL_ENABLE;
+}
+
 void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
 {
        csr_ops->build_csr_ring_base_addr = build_csr_ring_base_addr;
@@ -88,14 +197,35 @@ void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops)
        csr_ops->write_csr_ring_head = write_csr_ring_head;
        csr_ops->read_csr_ring_tail = read_csr_ring_tail;
        csr_ops->write_csr_ring_tail = write_csr_ring_tail;
+       csr_ops->read_csr_stat = read_csr_stat;
+       csr_ops->read_csr_uo_stat = read_csr_uo_stat;
        csr_ops->read_csr_e_stat = read_csr_e_stat;
+       csr_ops->read_csr_ne_stat = read_csr_ne_stat;
+       csr_ops->read_csr_nf_stat = read_csr_nf_stat;
+       csr_ops->read_csr_f_stat = read_csr_f_stat;
+       csr_ops->read_csr_c_stat = read_csr_c_stat;
+       csr_ops->read_csr_exp_stat = read_csr_exp_stat;
+       csr_ops->read_csr_exp_int_en = read_csr_exp_int_en;
+       csr_ops->write_csr_exp_int_en = write_csr_exp_int_en;
+       csr_ops->read_csr_ring_config = read_csr_ring_config;
        csr_ops->write_csr_ring_config = write_csr_ring_config;
+       csr_ops->read_csr_ring_base = read_csr_ring_base;
        csr_ops->write_csr_ring_base = write_csr_ring_base;
+       csr_ops->read_csr_int_en = read_csr_int_en;
+       csr_ops->write_csr_int_en = write_csr_int_en;
+       csr_ops->read_csr_int_flag = read_csr_int_flag;
        csr_ops->write_csr_int_flag = write_csr_int_flag;
+       csr_ops->read_csr_int_srcsel = read_csr_int_srcsel;
        csr_ops->write_csr_int_srcsel = write_csr_int_srcsel;
+       csr_ops->write_csr_int_srcsel_w_val = write_csr_int_srcsel_w_val;
+       csr_ops->read_csr_int_col_en = read_csr_int_col_en;
        csr_ops->write_csr_int_col_en = write_csr_int_col_en;
+       csr_ops->read_csr_int_col_ctl = read_csr_int_col_ctl;
        csr_ops->write_csr_int_col_ctl = write_csr_int_col_ctl;
+       csr_ops->read_csr_int_flag_and_col = read_csr_int_flag_and_col;
        csr_ops->write_csr_int_flag_and_col = write_csr_int_flag_and_col;
+       csr_ops->read_csr_ring_srv_arb_en = read_csr_ring_srv_arb_en;
        csr_ops->write_csr_ring_srv_arb_en = write_csr_ring_srv_arb_en;
+       csr_ops->get_int_col_ctl_enable_mask = get_int_col_ctl_enable_mask;
 }
 EXPORT_SYMBOL_GPL(adf_gen4_init_hw_csr_ops);

diff --git a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h
index 08d803432d9f133db2842361a162bb2a99e23b1f..6f33e7c87c2c90e81a2bc5d1dd6549b1ce5ff27d 100644 (file)
--- a/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h
+++ b/drivers/crypto/intel/qat/qat_common/adf_gen4_hw_csr_data.h
@@ -12,13 +12,22 @@
 #define ADF_RING_CSR_RING_UBASE                0x1080
 #define ADF_RING_CSR_RING_HEAD         0x0C0
 #define ADF_RING_CSR_RING_TAIL         0x100
+#define ADF_RING_CSR_STAT              0x140
+#define ADF_RING_CSR_UO_STAT           0x148
 #define ADF_RING_CSR_E_STAT            0x14C
+#define ADF_RING_CSR_NE_STAT           0x150
+#define ADF_RING_CSR_NF_STAT           0x154
+#define ADF_RING_CSR_F_STAT            0x158
+#define ADF_RING_CSR_C_STAT            0x15C
+#define ADF_RING_CSR_INT_FLAG_EN       0x16C
 #define ADF_RING_CSR_INT_FLAG          0x170
 #define ADF_RING_CSR_INT_SRCSEL                0x174
+#define ADF_RING_CSR_INT_COL_EN                0x17C
 #define ADF_RING_CSR_INT_COL_CTL       0x180
 #define ADF_RING_CSR_INT_FLAG_AND_COL  0x184
+#define ADF_RING_CSR_EXP_STAT          0x188
+#define ADF_RING_CSR_EXP_INT_EN                0x18C
 #define ADF_RING_CSR_INT_COL_CTL_ENABLE        0x80000000
-#define ADF_RING_CSR_INT_COL_EN                0x17C
 #define ADF_RING_CSR_ADDR_OFFSET       0x100000
 #define ADF_RING_BUNDLE_SIZE           0x2000
 #define ADF_RING_CSR_RING_SRV_ARB_EN   0x19C
@@ -33,9 +42,41 @@
        ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_RING_TAIL + ((ring) << 2))
+#define READ_CSR_STAT(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_STAT)
+#define READ_CSR_UO_STAT(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_UO_STAT)
 #define READ_CSR_E_STAT(csr_base_addr, bank) \
        ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
+#define READ_CSR_NE_STAT(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_NE_STAT)
+#define READ_CSR_NF_STAT(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_NF_STAT)
+#define READ_CSR_F_STAT(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_F_STAT)
+#define READ_CSR_C_STAT(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_C_STAT)
+#define READ_CSR_EXP_STAT(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_EXP_STAT)
+#define READ_CSR_EXP_INT_EN(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_EXP_INT_EN)
+#define WRITE_CSR_EXP_INT_EN(csr_base_addr, bank, value) \
+       ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + \
+                  ADF_RING_CSR_EXP_INT_EN, value)
+#define READ_CSR_RING_CONFIG(csr_base_addr, bank, ring) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + \
+                  ADF_RING_CSR_RING_CONFIG + ((ring) << 2))
 #define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
@@ -57,6 +98,25 @@ do { \
                   ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base);   \
 } while (0)
 
+static inline u64 read_base(void __iomem *csr_base_addr, u32 bank, u32 ring)
+{
+       u32 l_base, u_base;
+
+       /*
+        * Use special IO wrapper for ring base as LBASE and UBASE are
+        * not physically contigious
+        */
+       l_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) +
+                           ADF_RING_CSR_RING_LBASE + (ring << 2));
+       u_base = ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) +
+                           ADF_RING_CSR_RING_UBASE + (ring << 2));
+
+       return (u64)u_base << 32 | (u64)l_base;
+}
+
+#define READ_CSR_RING_BASE(csr_base_addr, bank, ring) \
+       read_base((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, (bank), (ring))
+
 #define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
@@ -65,28 +125,59 @@ do { \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
+#define READ_CSR_INT_EN(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_FLAG_EN)
+#define WRITE_CSR_INT_EN(csr_base_addr, bank, value) \
+       ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + \
+                  ADF_RING_CSR_INT_FLAG_EN, (value))
+#define READ_CSR_INT_FLAG(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_FLAG)
 #define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_INT_FLAG, (value))
+#define READ_CSR_INT_SRCSEL(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_SRCSEL)
 #define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK)
+#define WRITE_CSR_INT_SRCSEL_W_VAL(csr_base_addr, bank, value) \
+       ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + \
+                  ADF_RING_CSR_INT_SRCSEL, (value))
+#define READ_CSR_INT_COL_EN(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_COL_EN)
 #define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_INT_COL_EN, (value))
+#define READ_CSR_INT_COL_CTL(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_INT_COL_CTL)
 #define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_INT_COL_CTL, \
                   ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
+#define READ_CSR_INT_FLAG_AND_COL(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + \
+                  ADF_RING_CSR_INT_FLAG_AND_COL)
 #define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \
                   ADF_RING_CSR_INT_FLAG_AND_COL, (value))
 
+#define READ_CSR_RING_SRV_ARB_EN(csr_base_addr, bank) \
+       ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
+                  ADF_RING_BUNDLE_SIZE * (bank) + \
+                  ADF_RING_CSR_RING_SRV_ARB_EN)
 #define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \
        ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
                   ADF_RING_BUNDLE_SIZE * (bank) + \