arm64: dts: imx93-11x11-evk: add sleep pinctrl for eqos and fec

Add sleep pinctrl settings for EQoS and FEC to save power when suspend.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
index 29425ca2d7d66845bad5cdedfb5fa65ec70cfe96..3b1ab204bbbfdfb251e27fb2f989f005d8018913 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
@@ -181,8 +181,9 @@
 };
 
 &eqos {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "sleep";
        pinctrl-0 = <&pinctrl_eqos>;
+       pinctrl-1 = <&pinctrl_eqos_sleep>;
        phy-mode = "rgmii-id";
        phy-handle = <&ethphy1>;
        status = "okay";
@@ -201,8 +202,9 @@
 };
 
 &fec {
-       pinctrl-names = "default";
+       pinctrl-names = "default", "sleep";
        pinctrl-0 = <&pinctrl_fec>;
+       pinctrl-1 = <&pinctrl_fec_sleep>;
        phy-mode = "rgmii-id";
        phy-handle = <&ethphy2>;
        fsl,magic-packet;
@@ -413,6 +415,25 @@
                >;
        };
 
+       pinctrl_eqos_sleep: eqossleepgrp {
+               fsl,pins = <
+                       MX93_PAD_ENET1_MDC__GPIO4_IO00                          0x31e
+                       MX93_PAD_ENET1_MDIO__GPIO4_IO01                         0x31e
+                       MX93_PAD_ENET1_RD0__GPIO4_IO10                          0x31e
+                       MX93_PAD_ENET1_RD1__GPIO4_IO11                          0x31e
+                       MX93_PAD_ENET1_RD2__GPIO4_IO12                          0x31e
+                       MX93_PAD_ENET1_RD3__GPIO4_IO13                          0x31e
+                       MX93_PAD_ENET1_RXC__GPIO4_IO09                          0x31e
+                       MX93_PAD_ENET1_RX_CTL__GPIO4_IO08                       0x31e
+                       MX93_PAD_ENET1_TD0__GPIO4_IO05                          0x31e
+                       MX93_PAD_ENET1_TD1__GPIO4_IO04                          0x31e
+                       MX93_PAD_ENET1_TD2__GPIO4_IO03                          0x31e
+                       MX93_PAD_ENET1_TD3__GPIO4_IO02                          0x31e
+                       MX93_PAD_ENET1_TXC__GPIO4_IO07                          0x31e
+                       MX93_PAD_ENET1_TX_CTL__GPIO4_IO06                       0x31e
+               >;
+       };
+
        pinctrl_fec: fecgrp {
                fsl,pins = <
                        MX93_PAD_ENET2_MDC__ENET1_MDC                   0x57e
@@ -439,6 +460,25 @@
                >;
        };
 
+       pinctrl_fec_sleep: fecsleepgrp {
+               fsl,pins = <
+                       MX93_PAD_ENET2_MDC__GPIO4_IO14                  0x51e
+                       MX93_PAD_ENET2_MDIO__GPIO4_IO15                 0x51e
+                       MX93_PAD_ENET2_RD0__GPIO4_IO24                  0x51e
+                       MX93_PAD_ENET2_RD1__GPIO4_IO25                  0x51e
+                       MX93_PAD_ENET2_RD2__GPIO4_IO26                  0x51e
+                       MX93_PAD_ENET2_RD3__GPIO4_IO27                  0x51e
+                       MX93_PAD_ENET2_RXC__GPIO4_IO23                  0x51e
+                       MX93_PAD_ENET2_RX_CTL__GPIO4_IO22               0x51e
+                       MX93_PAD_ENET2_TD0__GPIO4_IO19                  0x51e
+                       MX93_PAD_ENET2_TD1__GPIO4_IO18                  0x51e
+                       MX93_PAD_ENET2_TD2__GPIO4_IO17                  0x51e
+                       MX93_PAD_ENET2_TD3__GPIO4_IO16                  0x51e
+                       MX93_PAD_ENET2_TXC__GPIO4_IO21                  0x51e
+                       MX93_PAD_ENET2_TX_CTL__GPIO4_IO20               0x51e
+               >;
+       };
+
        pinctrl_uart1: uart1grp {
                fsl,pins = <
                        MX93_PAD_UART1_RXD__LPUART1_RX                  0x31e