arm64: dts: fsl: ls1046a: disable uarts by default

Disable the UARTs by defaultto avoid registering unused UARTs. This
effectively change the number of registered UARTS for the RDB and QDS from
4 to 2 but this seems the right thing to do.

It is especially useful when connecting other 8250 uart on PCIe for example
as the default maximum number of 8250 UARTs that can be registered is 4.

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index cba0eacd18c21ec60d44676374591f9e2f7eb0c8..d0ee696e0466ad275713260347b25ad0316e4f97 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -425,6 +425,7 @@
                        reg = <0x00 0x21c0500 0x0 0x100>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clockgen 4 1>;
+                       status = "disabled";
                };
 
                duart1: serial@21c0600 {
@@ -432,6 +433,7 @@
                        reg = <0x00 0x21c0600 0x0 0x100>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clockgen 4 1>;
+                       status = "disabled";
                };
 
                duart2: serial@21d0500 {
@@ -439,6 +441,7 @@
                        reg = <0x0 0x21d0500 0x0 0x100>;
                        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clockgen 4 1>;
+                       status = "disabled";
                };
 
                duart3: serial@21d0600 {
@@ -446,6 +449,7 @@
                        reg = <0x0 0x21d0600 0x0 0x100>;
                        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&clockgen 4 1>;
+                       status = "disabled";
                };
 
                gpio0: gpio@2300000 {