drm/amdgpu: Clean up KFD VMID assignment

The KFD VMID assignment was hard-coded in a few places. Consolidate that in
a single variable adev->vm_manager.first_kfd_vmid. The value is still
assigned in gmc-ip-version-specific code.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index ad59ac4423b8bddb829d8a62d6101d85bdb0fe79..1b865fed74ca839efaf1953dd84cfdc85c142d89 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -31,8 +31,6 @@
 #include "amdgpu_xgmi.h"
 #include <uapi/linux/kfd_ioctl.h>
 
-static const unsigned int compute_vmid_bitmap = 0xFF00;
-
 /* Total memory size in system memory and all GPU VRAM. Used to
  * estimate worst case amount of memory to reserve for page tables
  */
@@ -113,7 +111,9 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
 
        if (adev->kfd.dev) {
                struct kgd2kfd_shared_resources gpu_resources = {
-                       .compute_vmid_bitmap = compute_vmid_bitmap,
+                       .compute_vmid_bitmap =
+                               ((1 << AMDGPU_NUM_VMID) - 1) -
+                               ((1 << adev->vm_manager.first_kfd_vmid) - 1),
                        .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
                        .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
                        .gpuvm_size = min(adev->vm_manager.max_pfn
@@ -637,10 +637,8 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
 
 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
 {
-       if (adev->kfd.dev) {
-               if ((1 << vmid) & compute_vmid_bitmap)
-                       return true;
-       }
+       if (adev->kfd.dev)
+               return vmid >= adev->vm_manager.first_kfd_vmid;
 
        return false;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 267fa45ddb660bfd95f90b3ddd30f518684b33cf..7521f4ab55de516c198a658a7819839945d47192 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -574,6 +574,9 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev)
                INIT_LIST_HEAD(&id_mgr->ids_lru);
                atomic_set(&id_mgr->reserved_vmid_num, 0);
 
+               /* manage only VMIDs not used by KFD */
+               id_mgr->num_ids = adev->vm_manager.first_kfd_vmid;
+
                /* skip over VMID 0, since it is the system VM */
                for (j = 1; j < id_mgr->num_ids; ++j) {
                        amdgpu_vmid_reset(adev, i, j);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index c8e68d7890bff92c3efdcb7a9d04e340bc950c6e..770025a5e500394bc9476dcc110bfe3c7036b9b3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -324,6 +324,7 @@ struct amdgpu_vm {
 struct amdgpu_vm_manager {
        /* Handling of VMIDs */
        struct amdgpu_vmid_mgr                  id_mgr[AMDGPU_MAX_VMHUBS];
+       unsigned int                            first_kfd_vmid;
 
        /* Handling of VM fences */
        u64                                     fence_context;

diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h
index 5f3f6ebfb3876222e69804bba5ffdc899c35288d..55982c0064b5600c02b17000cb55ccd48c193f3a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cikd.h
+++ b/drivers/gpu/drm/amd/amdgpu/cikd.h
@@ -54,8 +54,6 @@
 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN        0x12010001
 #define HAWAII_GB_ADDR_CONFIG_GOLDEN         0x12011003
 
-#define AMDGPU_NUM_OF_VMIDS    8
-
 #define                PIPEID(x)                                       ((x) << 0)
 #define                MEID(x)                                         ((x) << 2)
 #define                VMID(x)                                         ((x) << 4)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 323285eb1457d9099f4ad8b024e035d7b95042e4..8366c506a8b57aeb9975897f0174d8212f89b7f5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4512,8 +4512,6 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
 }
 
 #define DEFAULT_SH_MEM_BASES   (0x6000)
-#define FIRST_COMPUTE_VMID     (8)
-#define LAST_COMPUTE_VMID      (16)
 
 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
 {
@@ -4529,7 +4527,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
        sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
 
        mutex_lock(&adev->srbm_mutex);
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                nv_grbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
@@ -4540,7 +4538,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
 
        /* Initialize all compute VMIDs to have no GDS, GWS, or OA
           acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 4aec76049a60b5a8e425b27a02e081f20b6685fb..04eaf3a8fddba0ec118d5249af0d84d634e5006a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1850,8 +1850,6 @@ static void gfx_v7_0_setup_rb(struct amdgpu_device *adev)
  *
  */
 #define DEFAULT_SH_MEM_BASES   (0x6000)
-#define FIRST_COMPUTE_VMID     (8)
-#define LAST_COMPUTE_VMID      (16)
 static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
 {
        int i;
@@ -1869,7 +1867,7 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
                        SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
        sh_mem_config |= MTYPE_NONCACHED << SH_MEM_CONFIG__DEFAULT_MTYPE__SHIFT;
        mutex_lock(&adev->srbm_mutex);
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                cik_srbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                WREG32(mmSH_MEM_CONFIG, sh_mem_config);
@@ -1882,7 +1880,7 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
 
        /* Initialize all compute VMIDs to have no GDS, GWS, or OA
           acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
                WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
                WREG32(amdgpu_gds_reg_offset[i].gws, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index efb759b62d211498ff299e5cf2a6b75715be4eff..33f1c4a46ebe0b35f74c25a7173bfdbfa11543f4 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3686,8 +3686,6 @@ static void gfx_v8_0_setup_rb(struct amdgpu_device *adev)
  *
  */
 #define DEFAULT_SH_MEM_BASES   (0x6000)
-#define FIRST_COMPUTE_VMID     (8)
-#define LAST_COMPUTE_VMID      (16)
 static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
 {
        int i;
@@ -3710,7 +3708,7 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
                        SH_MEM_CONFIG__PRIVATE_ATC_MASK;
 
        mutex_lock(&adev->srbm_mutex);
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                vi_srbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                WREG32(mmSH_MEM_CONFIG, sh_mem_config);
@@ -3723,7 +3721,7 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
 
        /* Initialize all compute VMIDs to have no GDS, GWS, or OA
           acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
                WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
                WREG32(amdgpu_gds_reg_offset[i].gws, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 99ffc3e1fddc1a3f9e910e00914b9df8b01021c4..cb9d60a4e05ed50004c6e731050a450ca98ba5a0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2463,8 +2463,6 @@ static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
 }
 
 #define DEFAULT_SH_MEM_BASES   (0x6000)
-#define FIRST_COMPUTE_VMID     (8)
-#define LAST_COMPUTE_VMID      (16)
 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
 {
        int i;
@@ -2484,7 +2482,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
                        SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
 
        mutex_lock(&adev->srbm_mutex);
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                soc15_grbm_select(adev, 0, 0, 0, i);
                /* CP and shaders */
                WREG32_SOC15_RLC(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
@@ -2495,7 +2493,7 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
 
        /* Initialize all compute VMIDs to have no GDS, GWS, or OA
           acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
+       for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index f7e66bf0f647ae3cde5f2c5849963a9e596f6206..bfe62985afffe1de626edfe2fc9ad5f994100931 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -49,8 +49,6 @@
 #include "mmhub_v2_0.h"
 #include "athub_v2_0.h"
 #include "athub_v2_1.h"
-/* XXX Move this macro to navi10 header file, which is like vid.h for VI.*/
-#define AMDGPU_NUM_OF_VMIDS                    8
 
 #if 0
 static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
@@ -905,8 +903,7 @@ static int gmc_v10_0_sw_init(void *handle)
         * amdgpu graphics/compute will use VMIDs 1-7
         * amdkfd will use VMIDs 8-15
         */
-       adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
-       adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
+       adev->vm_manager.first_kfd_vmid = 8;
 
        amdgpu_vm_manager_init(adev);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index a75e472b4a81ea8494eb4341b606b409d8cea594..538e7ee35cdf2d7c7f374e04e23213fb4e1ae6c2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -878,7 +878,7 @@ static int gmc_v6_0_sw_init(void *handle)
         * amdgpu graphics/compute will use VMIDs 1-7
         * amdkfd will use VMIDs 8-15
         */
-       adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
+       adev->vm_manager.first_kfd_vmid = 8;
        amdgpu_vm_manager_init(adev);
 
        /* base offset of vram pages */

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index bcd4baecfe115c15f4a35b5b7a313b1c199d2574..e18296dc13861d0eaee699bb0da6652948456d27 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1052,7 +1052,7 @@ static int gmc_v7_0_sw_init(void *handle)
         * amdgpu graphics/compute will use VMIDs 1-7
         * amdkfd will use VMIDs 8-15
         */
-       adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
+       adev->vm_manager.first_kfd_vmid = 8;
        amdgpu_vm_manager_init(adev);
 
        /* base offset of vram pages */

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 26976e50e2a2917c2762bb9a6fe78b3b4a4e1744..a9e722b8a45833b83dfa95d7dd33d3fb24f35018 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1177,7 +1177,7 @@ static int gmc_v8_0_sw_init(void *handle)
         * amdgpu graphics/compute will use VMIDs 1-7
         * amdkfd will use VMIDs 8-15
         */
-       adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
+       adev->vm_manager.first_kfd_vmid = 8;
        amdgpu_vm_manager_init(adev);
 
        /* base offset of vram pages */

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 11e93a82131def7ee7f231d1f29b06e81cddaaf4..6e10b42c57e5e3f0151389b548da0b311ed0855b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -68,9 +68,6 @@
 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK                                          0x00003FFFL
 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK                                         0x3FFF0000L
 
-/* XXX Move this macro to VEGA10 header file, which is like vid.h for VI.*/
-#define AMDGPU_NUM_OF_VMIDS                    8
-
 static const u32 golden_settings_vega10_hdp[] =
 {
        0xf64, 0x0fffffff, 0x00000000,
@@ -1251,9 +1248,7 @@ static int gmc_v9_0_sw_init(void *handle)
         * amdgpu graphics/compute will use VMIDs 1-7
         * amdkfd will use VMIDs 8-15
         */
-       adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
-       adev->vm_manager.id_mgr[AMDGPU_MMHUB_0].num_ids = AMDGPU_NUM_OF_VMIDS;
-       adev->vm_manager.id_mgr[AMDGPU_MMHUB_1].num_ids = AMDGPU_NUM_OF_VMIDS;
+       adev->vm_manager.first_kfd_vmid = 8;
 
        amdgpu_vm_manager_init(adev);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h
index 790ba46eaebbbf675a82a39f34ccfc2eb6d21fb9..4e935baa7b912cb3ce117ed1487f83f9e7560637 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si_enums.h
+++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h
@@ -121,7 +121,6 @@
 #define CURSOR_UPDATE_LOCK             (1 << 16)
 #define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
 
-#define AMDGPU_NUM_OF_VMIDS                     8
 #define SI_CRTC0_REGISTER_OFFSET                0
 #define SI_CRTC1_REGISTER_OFFSET                0x300
 #define SI_CRTC2_REGISTER_OFFSET                0x2600

diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index b3e2dbaf7bd740f531a98de1e14df1460cd798f9..9a39cbfe6db9f277adc5576caa4dcd0d2ddff4fe 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -49,8 +49,6 @@
 #define SI_MAX_TCC_MASK                0xFFFF
 #define SI_MAX_CTLACKS_ASSERTION_WAIT   100
 
-#define AMDGPU_NUM_OF_VMIDS            8
-
 /* SMC IND accessor regs */
 #define SMC_IND_INDEX_0                              0x80
 #define SMC_IND_DATA_0                               0x81

diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index 7a01e6133798014e9a5e290fa9d3d8003af21069..80ce42aacc0cce3d7819c8037f27ddf0f9e8aa86 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -67,8 +67,6 @@
 #define HPD4_REGISTER_OFFSET                 (0x18b8 - 0x1898)
 #define HPD5_REGISTER_OFFSET                 (0x18c0 - 0x1898)
 
-#define AMDGPU_NUM_OF_VMIDS                    8
-
 #define                PIPEID(x)                                       ((x) << 0)
 #define                MEID(x)                                         ((x) << 2)
 #define                VMID(x)                                         ((x) << 4)