net/mlx5e: Fix endianness handling in pedit mask

The mask value is provided as 64 bit and has to be casted in
either 32 or 16 bit. On big endian systems the wrong half was
casted which resulted in an all zero mask.

Fixes: 2b64beba0251 ("net/mlx5e: Support header re-write of partial fields in TC pedit offload")
Signed-off-by: Sebastian Hense <sebastian.hense1@ibm.com>
Reviewed-by: Roi Dayan <roid@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
index 74091f72c9a8ab44ecc9e5b25f9ce63b2919f3e7..ec5fc52bf5721e9493e7f6e429c3f1579259339c 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_tc.c
@@ -2476,10 +2476,11 @@ static int offload_pedit_fields(struct pedit_headers_action *hdrs,
                        continue;
 
                if (f->field_bsize == 32) {
-                       mask_be32 = *(__be32 *)&mask;
+                       mask_be32 = (__be32)mask;
                        mask = (__force unsigned long)cpu_to_le32(be32_to_cpu(mask_be32));
                } else if (f->field_bsize == 16) {
-                       mask_be16 = *(__be16 *)&mask;
+                       mask_be32 = (__be32)mask;
+                       mask_be16 = *(__be16 *)&mask_be32;
                        mask = (__force unsigned long)cpu_to_le16(be16_to_cpu(mask_be16));
                }