drm/amdgpu: Clean sdma wptr register when only enable wptr polling

The sdma wptr polling memory is not fast enough, then the sdma
wptr register will be random, and not equal to sdma rptr, which
will cause sdma engine hang when load driver, so clean up the sdma
wptr directly to fix this issue.

v2:add comment above the code and correct coding style

Reviewed-by: Xiangliang Yu <Xiangliang.Yu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 9c4efd4effc64f1ce192a58db0d065281195f919..ecaef084dab14c081b90760f722d29240bcfd692 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -711,14 +711,17 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
                WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
                       upper_32_bits(wptr_gpu_addr));
                wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
-               if (ring->use_pollmem)
+               if (ring->use_pollmem) {
+                       /*wptr polling is not enogh fast, directly clean the wptr register */
+                       WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
                        wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
                                                       SDMA0_GFX_RB_WPTR_POLL_CNTL,
                                                       ENABLE, 1);
-               else
+               } else {
                        wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
                                                       SDMA0_GFX_RB_WPTR_POLL_CNTL,
                                                       ENABLE, 0);
+               }
                WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 
                /* enable DMA RB */