}
 EXPORT_SYMBOL(intel_gtt_get);
 
+void intel_gtt_chipset_flush(void)
+{
+       if (intel_private.driver->chipset_flush)
+               intel_private.driver->chipset_flush();
+}
+EXPORT_SYMBOL(intel_gtt_chipset_flush);
+
 void intel_gmch_remove(struct pci_dev *pdev)
 {
        if (intel_private.pcidev)
 
        drm_i915_private_t *dev_priv = dev->dev_private;
 
        if (flush_domains & I915_GEM_DOMAIN_CPU)
-               drm_agp_chipset_flush(dev);
+               intel_gtt_chipset_flush();
 
        if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
                if (flush_rings & RING_RENDER)
 static void
 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
 {
-       struct drm_device *dev = obj->dev;
        uint32_t old_write_domain;
 
        if (obj->write_domain != I915_GEM_DOMAIN_CPU)
                return;
 
        i915_gem_clflush_object(obj);
-       drm_agp_chipset_flush(dev);
+       intel_gtt_chipset_flush();
        old_write_domain = obj->write_domain;
        obj->write_domain = 0;
 
                        page_cache_release(page);
                }
        }
-       drm_agp_chipset_flush(dev);
+       intel_gtt_chipset_flush();
 
        obj_priv->phys_obj->cur_obj = NULL;
        obj_priv->phys_obj = NULL;
                        return -EFAULT;
        }
 
-       drm_agp_chipset_flush(dev);
+       intel_gtt_chipset_flush();
        return 0;
 }
 
 
        unsigned int gtt_mappable_entries;
 } *intel_gtt_get(void);
 
+void intel_gtt_chipset_flush(void);
 
 /* Special gtt memory types */
 #define AGP_DCACHE_MEMORY      1
 #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3)
 
 #endif
-