soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflict
authorAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tue, 21 Nov 2023 12:50:26 +0000 (13:50 +0100)
committerAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Mon, 11 Dec 2023 10:36:12 +0000 (11:36 +0100)
The svs_regs_v2 array of registers was offsetted by 0xc00 because the
SVS node was supposed to have the same iostart as the thermal sensors.
That's wrong for two reasons:
 1. Two different devices cannot have the same iostart in devicetree,
    as those would technically be the same device otherwise; and
 2. SVS and Thermal Sensor (be it LVTS or AUXADC thermal) are not the
    same IP, and those two do obviously have a different iospace.

Even though there already are users of this register array, the only
one that declares a devicetree node for SVS is MT8183 - but it never
actually worked because the "tzts1" thermal zone missed thermal trips,
hence this driver's probe always failed on that SoC.

Knowing this - it is safe to say that keeping compatibility with older
device trees is pointless, hence simply subtract the 0xc00 offset from
the register offset array.

Link: https://lore.kernel.org/r/20231121125044.78642-3-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
drivers/soc/mediatek/mtk-svs.c

index 0f7cfbe5630bb32ecb5d7b2b10ba9baba63134d4..416e9b313c0add34adc65f1b696d0f2052453bdd 100644 (file)
@@ -256,60 +256,60 @@ enum svs_reg_index {
 };
 
 static const u32 svs_regs_v2[] = {
-       [DESCHAR]               = 0xc00,
-       [TEMPCHAR]              = 0xc04,
-       [DETCHAR]               = 0xc08,
-       [AGECHAR]               = 0xc0c,
-       [DCCONFIG]              = 0xc10,
-       [AGECONFIG]             = 0xc14,
-       [FREQPCT30]             = 0xc18,
-       [FREQPCT74]             = 0xc1c,
-       [LIMITVALS]             = 0xc20,
-       [VBOOT]                 = 0xc24,
-       [DETWINDOW]             = 0xc28,
-       [CONFIG]                = 0xc2c,
-       [TSCALCS]               = 0xc30,
-       [RUNCONFIG]             = 0xc34,
-       [SVSEN]                 = 0xc38,
-       [INIT2VALS]             = 0xc3c,
-       [DCVALUES]              = 0xc40,
-       [AGEVALUES]             = 0xc44,
-       [VOP30]                 = 0xc48,
-       [VOP74]                 = 0xc4c,
-       [TEMP]                  = 0xc50,
-       [INTSTS]                = 0xc54,
-       [INTSTSRAW]             = 0xc58,
-       [INTEN]                 = 0xc5c,
-       [CHKINT]                = 0xc60,
-       [CHKSHIFT]              = 0xc64,
-       [STATUS]                = 0xc68,
-       [VDESIGN30]             = 0xc6c,
-       [VDESIGN74]             = 0xc70,
-       [DVT30]                 = 0xc74,
-       [DVT74]                 = 0xc78,
-       [AGECOUNT]              = 0xc7c,
-       [SMSTATE0]              = 0xc80,
-       [SMSTATE1]              = 0xc84,
-       [CTL0]                  = 0xc88,
-       [DESDETSEC]             = 0xce0,
-       [TEMPAGESEC]            = 0xce4,
-       [CTRLSPARE0]            = 0xcf0,
-       [CTRLSPARE1]            = 0xcf4,
-       [CTRLSPARE2]            = 0xcf8,
-       [CTRLSPARE3]            = 0xcfc,
-       [CORESEL]               = 0xf00,
-       [THERMINTST]            = 0xf04,
-       [INTST]                 = 0xf08,
-       [THSTAGE0ST]            = 0xf0c,
-       [THSTAGE1ST]            = 0xf10,
-       [THSTAGE2ST]            = 0xf14,
-       [THAHBST0]              = 0xf18,
-       [THAHBST1]              = 0xf1c,
-       [SPARE0]                = 0xf20,
-       [SPARE1]                = 0xf24,
-       [SPARE2]                = 0xf28,
-       [SPARE3]                = 0xf2c,
-       [THSLPEVEB]             = 0xf30,
+       [DESCHAR]               = 0x00,
+       [TEMPCHAR]              = 0x04,
+       [DETCHAR]               = 0x08,
+       [AGECHAR]               = 0x0c,
+       [DCCONFIG]              = 0x10,
+       [AGECONFIG]             = 0x14,
+       [FREQPCT30]             = 0x18,
+       [FREQPCT74]             = 0x1c,
+       [LIMITVALS]             = 0x20,
+       [VBOOT]                 = 0x24,
+       [DETWINDOW]             = 0x28,
+       [CONFIG]                = 0x2c,
+       [TSCALCS]               = 0x30,
+       [RUNCONFIG]             = 0x34,
+       [SVSEN]                 = 0x38,
+       [INIT2VALS]             = 0x3c,
+       [DCVALUES]              = 0x40,
+       [AGEVALUES]             = 0x44,
+       [VOP30]                 = 0x48,
+       [VOP74]                 = 0x4c,
+       [TEMP]                  = 0x50,
+       [INTSTS]                = 0x54,
+       [INTSTSRAW]             = 0x58,
+       [INTEN]                 = 0x5c,
+       [CHKINT]                = 0x60,
+       [CHKSHIFT]              = 0x64,
+       [STATUS]                = 0x68,
+       [VDESIGN30]             = 0x6c,
+       [VDESIGN74]             = 0x70,
+       [DVT30]                 = 0x74,
+       [DVT74]                 = 0x78,
+       [AGECOUNT]              = 0x7c,
+       [SMSTATE0]              = 0x80,
+       [SMSTATE1]              = 0x84,
+       [CTL0]                  = 0x88,
+       [DESDETSEC]             = 0xe0,
+       [TEMPAGESEC]            = 0xe4,
+       [CTRLSPARE0]            = 0xf0,
+       [CTRLSPARE1]            = 0xf4,
+       [CTRLSPARE2]            = 0xf8,
+       [CTRLSPARE3]            = 0xfc,
+       [CORESEL]               = 0x300,
+       [THERMINTST]            = 0x304,
+       [INTST]                 = 0x308,
+       [THSTAGE0ST]            = 0x30c,
+       [THSTAGE1ST]            = 0x310,
+       [THSTAGE2ST]            = 0x314,
+       [THAHBST0]              = 0x318,
+       [THAHBST1]              = 0x31c,
+       [SPARE0]                = 0x320,
+       [SPARE1]                = 0x324,
+       [SPARE2]                = 0x328,
+       [SPARE3]                = 0x32c,
+       [THSLPEVEB]             = 0x330,
 };
 
 /**