net: phy: dp83867: Extend RX strap quirk for SGMII mode

[ Upstream commit 0c9efbd5c50c64ead434960a404c9c9a097b0403 ]

When RX strap in HW is not set to MODE 3 or 4, bit 7 and 8 in CF4
register should be set. The former is already handled in
dp83867_config_init; add the latter in SGMII specific initialization.

Fixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy")
Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index d097097c93c39bcbeb4389641cf403605dc55be6..783e30451e30d42831b3e414aad60c2063791e60 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -791,6 +791,14 @@ static int dp83867_config_init(struct phy_device *phydev)
                else
                        val &= ~DP83867_SGMII_TYPE;
                phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
+
+               /* This is a SW workaround for link instability if RX_CTRL is
+                * not strapped to mode 3 or 4 in HW. This is required for SGMII
+                * in addition to clearing bit 7, handled above.
+                */
+               if (dp83867->rxctrl_strap_quirk)
+                       phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
+                                        BIT(8));
        }
 
        val = phy_read(phydev, DP83867_CFG3);