return r;
 }
 
+int amdgpu_ras_block_late_init_default(struct amdgpu_device *adev,
+                        struct ras_common_if *ras_block)
+{
+       return amdgpu_ras_block_late_init(adev, ras_block);
+}
+
 /* helper function to remove ras fs node and interrupt handler */
 void amdgpu_ras_block_late_fini(struct amdgpu_device *adev,
                          struct ras_common_if *ras_block)
                        dev_warn(adev->dev, "Warning: abnormal ras list node.\n");
                        continue;
                }
+
                obj = node->ras_obj;
                if (obj->ras_late_init) {
                        r = obj->ras_late_init(adev, &obj->ras_comm);
                                        obj->ras_comm.name, r);
                                return r;
                        }
-               }
+               } else
+                       amdgpu_ras_block_late_init_default(adev, &obj->ras_comm);
        }
 
        return 0;
 
                adev->mmhub.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
                adev->mmhub.ras_if = &adev->mmhub.ras->ras_block.ras_comm;
 
-               /* If don't define special ras_late_init function, use default ras_late_init */
-               if (!adev->mmhub.ras->ras_block.ras_late_init)
-                       adev->mmhub.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
-
                /* If don't define special ras_fini function, use default ras_fini */
                if (!adev->mmhub.ras->ras_block.ras_fini)
                        adev->mmhub.ras->ras_block.ras_fini = amdgpu_mmhub_ras_fini;
 
                        .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
                },
                .hw_ops = &hdp_v4_0_ras_hw_ops,
-               .ras_late_init = amdgpu_ras_block_late_init,
                .ras_fini = amdgpu_hdp_ras_fini,
        },
 };
 
                },
                .hw_ops = &mca_v3_0_mp0_hw_ops,
                .ras_block_match = mca_v3_0_ras_block_match,
-               .ras_late_init = amdgpu_ras_block_late_init,
                .ras_fini = mca_v3_0_mp0_ras_fini,
        },
 };
                },
                .hw_ops = &mca_v3_0_mp1_hw_ops,
                .ras_block_match = mca_v3_0_ras_block_match,
-               .ras_late_init = amdgpu_ras_block_late_init,
                .ras_fini = mca_v3_0_mp1_ras_fini,
        },
 };
                },
                .hw_ops = &mca_v3_0_mpio_hw_ops,
                .ras_block_match = mca_v3_0_ras_block_match,
-               .ras_late_init = amdgpu_ras_block_late_init,
                .ras_fini = mca_v3_0_mpio_ras_fini,
        },
 };