arm64: dts: zynqmp: Wire arasan nand controller
authorMichal Simek <michal.simek@xilinx.com>
Thu, 21 Jan 2021 10:26:56 +0000 (11:26 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Mon, 1 Feb 2021 09:36:32 +0000 (10:36 +0100)
Add missing arasan controller with clocks. Disable it by default. Every
board can enable it with specifying others properties.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/05cc1ce7973ac5200aeca428c137b422c827c5e8.1611224800.git.michal.simek@xilinx.com
arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi
arch/arm64/boot/dts/xilinx/zynqmp.dtsi

index c94c3bb67edcb3fe96364b25e5e2ac3d1f5a7208..7af57619436d8cf0aba0a66159324674543d0849 100644 (file)
        clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
 };
 
+&nand0 {
+       clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
+};
+
 &gem0 {
        clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
                 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
index 31c6943c6217052140e02e017ca6b2c20e1a0ea7..19b349f00ce78ff7f086fbec4d9bbe4c81e4272d 100644 (file)
                        interrupts = <0 112 4>;
                };
 
+               nand0: nand-controller@ff100000 {
+                       compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
+                       status = "disabled";
+                       reg = <0x0 0xff100000 0x0 0x1000>;
+                       clock-names = "controller", "bus";
+                       interrupt-parent = <&gic>;
+                       interrupts = <0 14 4>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       power-domains = <&zynqmp_firmware PD_NAND>;
+               };
+
                gem0: ethernet@ff0b0000 {
                        compatible = "cdns,zynqmp-gem", "cdns,gem";
                        status = "disabled";