coresight: etm4x: Expose trcdevarch via sysfs
authorSuzuki K Poulose <suzuki.poulose@arm.com>
Mon, 1 Feb 2021 18:13:42 +0000 (11:13 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 4 Feb 2021 16:00:33 +0000 (17:00 +0100)
Expose the TRCDEVARCH register via the sysfs for component
detection. Given that the TRCIDR1 may not completely identify
the ETM component and instead need to use TRCDEVARCH, expose
this via sysfs for tools to use it for identification.

Link: https://lore.kernel.org/r/20210110224850.1880240-21-suzuki.poulose@arm.com
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-23-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
drivers/hwtracing/coresight/coresight-etm4x-sysfs.c

index 881f0cd99ce4ed7c894ec4bc35c59bf8dc7f1ecc..8e53a32f815056f97220b2092249128c12a848d0 100644 (file)
@@ -371,6 +371,14 @@ Contact:   Mathieu Poirier <mathieu.poirier@linaro.org>
 Description:   (Read) Print the content of the Device ID Register
                (0xFC8).  The value is taken directly from the HW.
 
+What:          /sys/bus/coresight/devices/etm<N>/mgmt/trcdevarch
+Date:          January 2021
+KernelVersion: 5.12
+Contact:       Mathieu Poirier <mathieu.poirier@linaro.org>
+Description:   (Read) Print the content of the Device Architecture Register
+               (offset 0xFBC).  The value is taken directly read
+               from the HW.
+
 What:          /sys/bus/coresight/devices/etm<N>/mgmt/trcdevtype
 Date:          April 2015
 KernelVersion: 4.01
index 45aeeac2f50eca7d1a3b0ef2641bf6573bbdca99..b646d53a313376d5ef617d6427e6169f7cebc3a8 100644 (file)
@@ -2442,6 +2442,7 @@ static struct attribute *coresight_etmv4_mgmt_attrs[] = {
        coresight_etm4x_reg(trcoslsr, TRCOSLSR),
        coresight_etm4x_reg(trcconfig, TRCCONFIGR),
        coresight_etm4x_reg(trctraceid, TRCTRACEIDR),
+       coresight_etm4x_reg(trcdevarch, TRCDEVARCH),
        NULL,
 };