ASSERT_EQ(0, self->check);
 }
 
+TEST_F(user, perf_empty_events) {
+       struct perf_event_attr pe = {0};
+       struct user_reg reg = {0};
+       struct perf_event_mmap_page *perf_page;
+       int page_size = sysconf(_SC_PAGESIZE);
+       int id, fd;
+       __u32 *val;
+
+       reg.size = sizeof(reg);
+       reg.name_args = (__u64)"__test_event";
+       reg.enable_bit = 31;
+       reg.enable_addr = (__u64)&self->check;
+       reg.enable_size = sizeof(self->check);
+
+       /* Register should work */
+       ASSERT_EQ(0, ioctl(self->data_fd, DIAG_IOCSREG, ®));
+       ASSERT_EQ(0, reg.write_index);
+       ASSERT_EQ(0, self->check);
+
+       /* Id should be there */
+       id = get_id();
+       ASSERT_NE(-1, id);
+
+       pe.type = PERF_TYPE_TRACEPOINT;
+       pe.size = sizeof(pe);
+       pe.config = id;
+       pe.sample_type = PERF_SAMPLE_RAW;
+       pe.sample_period = 1;
+       pe.wakeup_events = 1;
+
+       /* Tracepoint attach should work */
+       fd = perf_event_open(&pe, 0, -1, -1, 0);
+       ASSERT_NE(-1, fd);
+
+       perf_page = mmap(NULL, page_size * 2, PROT_READ, MAP_SHARED, fd, 0);
+       ASSERT_NE(MAP_FAILED, perf_page);
+
+       /* Status should be updated */
+       ASSERT_EQ(1 << reg.enable_bit, self->check);
+
+       /* Ensure write shows up at correct offset */
+       ASSERT_NE(-1, write(self->data_fd, ®.write_index,
+                                       sizeof(reg.write_index)));
+       val = (void *)(((char *)perf_page) + perf_page->data_offset);
+       ASSERT_EQ(PERF_RECORD_SAMPLE, *val);
+
+       munmap(perf_page, page_size * 2);
+       close(fd);
+
+       /* Status should be updated */
+       ASSERT_EQ(0, self->check);
+}
+
 int main(int argc, char **argv)
 {
        return test_harness_run(argc, argv);