arm64: dts: qcom: sc7280: fix display port phy reg property

Existing display port phy reg property is derived from usb phy which
map display port phy pcs to wrong address which cause aux init
with wrong address and prevent both dpcd read and write from working.
Fix this problem by assigning correct pcs address to display port
phy reg property.

Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes")
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1631216998-10049-1-git-send-email-khsieh@codeaurora.org

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 53a21d0861787b50e0812c93d90fb6b565dcd9ca..1c5e4565e88b06e0df32f52c71a17cec8e7d3670 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -1258,15 +1258,11 @@
                        dp_phy: dp-phy@88ea200 {
                                reg = <0 0x088ea200 0 0x200>,
                                      <0 0x088ea400 0 0x200>,
-                                     <0 0x088eac00 0 0x400>,
+                                     <0 0x088eaa00 0 0x200>,
                                      <0 0x088ea600 0 0x200>,
-                                     <0 0x088ea800 0 0x200>,
-                                     <0 0x088eaa00 0 0x100>;
+                                     <0 0x088ea800 0 0x200>;
                                #phy-cells = <0>;
                                #clock-cells = <1>;
-                               clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
-                               clock-names = "pipe0";
-                               clock-output-names = "usb3_phy_pipe_clk_src";
                        };
                };