riscv: dts: sophgo: cv18xx: Add spi devices

Add spi devices for the CV180x, CV181x and SG200x soc.

Link: https://lore.kernel.org/r/IA1PR20MB49532705DE532BCF81CCEFD0BB442@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index dc6452a2fe0139f1cec69f1c30133936982b6db0..dcb219d9d2faa989dc8b68fba920d8df8de8bc0c 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -184,6 +184,50 @@
                        status = "disabled";
                };
 
+               spi0: spi@4180000 {
+                       compatible = "snps,dw-apb-ssi";
+                       reg = <0x04180000 0x10000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
+                       clock-names = "ssi_clk", "pclk";
+                       interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               spi1: spi@4190000 {
+                       compatible = "snps,dw-apb-ssi";
+                       reg = <0x04190000 0x10000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
+                       clock-names = "ssi_clk", "pclk";
+                       interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               spi2: spi@41a0000 {
+                       compatible = "snps,dw-apb-ssi";
+                       reg = <0x041a0000 0x10000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
+                       clock-names = "ssi_clk", "pclk";
+                       interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
+               spi3: spi@41b0000 {
+                       compatible = "snps,dw-apb-ssi";
+                       reg = <0x041b0000 0x10000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
+                       clock-names = "ssi_clk", "pclk";
+                       interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+               };
+
                uart4: serial@41c0000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x041c0000 0x100>;