accel/habanalabs: fix ETR/ETF flush logic

When config_etr or config_etf are called we need to validate the
parameters that are passed into them to make sure the requested
operation is valid.

Signed-off-by: Benjamin Dotan <bdotan@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>

diff --git a/drivers/accel/habanalabs/gaudi/gaudi_coresight.c b/drivers/accel/habanalabs/gaudi/gaudi_coresight.c
index 3455b14554c677e2f8396a328081ef3facb8db0b..1168fefa33f48494cd7a1a19412e47d192054058 100644 (file)
--- a/drivers/accel/habanalabs/gaudi/gaudi_coresight.c
+++ b/drivers/accel/habanalabs/gaudi/gaudi_coresight.c
@@ -482,6 +482,11 @@ static int gaudi_config_etf(struct hl_device *hdev,
 
        WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
 
+       val = RREG32(base_reg + 0x20);
+
+       if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+               return 0;
+
        val = RREG32(base_reg + 0x304);
        val |= 0x1000;
        WREG32(base_reg + 0x304, val);
@@ -580,6 +585,13 @@ static int gaudi_config_etr(struct hl_device *hdev,
 
        WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
 
+       val = RREG32(mmPSOC_ETR_CTL);
+
+       if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+               return 0;
+
+
+
        val = RREG32(mmPSOC_ETR_FFCR);
        val |= 0x1000;
        WREG32(mmPSOC_ETR_FFCR, val);

diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
index 3e90bc9692646a3b71f2be9732873d107d20bbe1..32e0f1a85b352bc1520c5536d57a520c9371c172 100644 (file)
--- a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
+++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c
@@ -2092,6 +2092,11 @@ static int gaudi2_config_etf(struct hl_device *hdev, struct hl_debug_params *par
        if (rc)
                return -EIO;
 
+       val = RREG32(base_reg + mmETF_CTL_OFFSET);
+
+       if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+               return 0;
+
        val = RREG32(base_reg + mmETF_FFCR_OFFSET);
        val |= 0x1000;
        WREG32(base_reg + mmETF_FFCR_OFFSET, val);
@@ -2189,6 +2194,11 @@ static int gaudi2_config_etr(struct hl_device *hdev, struct hl_ctx *ctx,
        if (rc)
                return -EIO;
 
+       val = RREG32(mmPSOC_ETR_CTL);
+
+       if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+               return 0;
+
        val = RREG32(mmPSOC_ETR_FFCR);
        val |= 0x1000;
        WREG32(mmPSOC_ETR_FFCR, val);

diff --git a/drivers/accel/habanalabs/goya/goya_coresight.c b/drivers/accel/habanalabs/goya/goya_coresight.c
index a6d6cc38bcd845fb3c51a17f001940827105a911..41cae5fd843b88bf3de894444281a227f9acd492 100644 (file)
--- a/drivers/accel/habanalabs/goya/goya_coresight.c
+++ b/drivers/accel/habanalabs/goya/goya_coresight.c
@@ -315,6 +315,11 @@ static int goya_config_etf(struct hl_device *hdev,
 
        WREG32(base_reg + 0xFB0, CORESIGHT_UNLOCK);
 
+       val = RREG32(base_reg + 0x20);
+
+       if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+               return 0;
+
        val = RREG32(base_reg + 0x304);
        val |= 0x1000;
        WREG32(base_reg + 0x304, val);
@@ -386,6 +391,11 @@ static int goya_config_etr(struct hl_device *hdev,
 
        WREG32(mmPSOC_ETR_LAR, CORESIGHT_UNLOCK);
 
+       val = RREG32(mmPSOC_ETR_CTL);
+
+       if ((!params->enable && val == 0x0) || (params->enable && val != 0x0))
+               return 0;
+
        val = RREG32(mmPSOC_ETR_FFCR);
        val |= 0x1000;
        WREG32(mmPSOC_ETR_FFCR, val);