x86/split_lock: Add Icelake microserver and Tigerlake CPU models

Icelake microserver CPU supports split lock detection while it doesn't
have the split lock enumeration bit in IA32_CORE_CAPABILITIES. Tigerlake
CPUs do enumerate the MSR.

 [ bp: Merge the two model-adding patches into one. ]

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Link: https://lkml.kernel.org/r/1588290395-2677-1-git-send-email-fenghua.yu@intel.com

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index a19a680542ce736ce0f89c3621d0695a9481c6f8..6abbcc774b82186d9ddfca92d170c51cfda482bc 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -1135,9 +1135,12 @@ void switch_to_sld(unsigned long tifn)
 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,           0),
        X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           0),
+       X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,           0),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,        1),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D,      1),
        X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      1),
+       X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,         1),
+       X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,           1),
        {}
 };