arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector
authorJosua Mayer <josua@solid-run.com>
Tue, 27 Feb 2024 16:23:11 +0000 (17:23 +0100)
committerGregory CLEMENT <gregory.clement@bootlin.com>
Fri, 1 Mar 2024 15:34:51 +0000 (16:34 +0100)
Clearfog GTR L8 has an extra SFP connector on the managed switch port 9.
Add descriptions for both entities along with pinctrl.

Signed-off-by: Josua Mayer <josua@solid-run.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr-l8.dts
arch/arm/boot/dts/marvell/armada-385-clearfog-gtr.dtsi

index 7075b57820d4b646e25387d19f4133f3911f78ca..1d6cfb975f4823879a33f5c2a54829e690a97b1f 100644 (file)
@@ -6,6 +6,16 @@
        model = "SolidRun Clearfog GTR L8";
        compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
                     "marvell,armada380";
+
+       /* CON25 */
+       sfp1: sfp-1 {
+               compatible = "sff,sfp";
+               pinctrl-0 = <&cf_gtr_sfp1_pins>;
+               pinctrl-names = "default";
+               i2c-bus = <&i2c0>;
+               mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
+               tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+       };
 };
 
 &mdio {
                                phy-handle = <&switch0phy7>;
                        };
 
+                       ethernet-port@9 {
+                               reg = <9>;
+                               label = "lan-sfp";
+                               phy-mode = "sgmii";
+                               sfp = <&sfp1>;
+                               managed = "in-band-status";
+                       };
+
                        ethernet-port@10 {
                                reg = <10>;
                                phy-mode = "2500base-x";
-
                                ethernet = <&eth1>;
+
                                fixed-link {
                                        speed = <2500>;
                                        full-duplex;
index 39ac97edb46387814f8cecc176962ff12a842c8a..f3a3cb6ac31148360d84b2231a43c7ca5bb015de 100644 (file)
                                        marvell,function = "gpio";
                                };
 
+                               cf_gtr_sfp1_pins: sfp1-pins {
+                                       /* sfp modabs, txdisable */
+                                       marvell,pins = "mpp24", "mpp54";
+                                       marvell,function = "gpio";
+                               };
+
                                cf_gtr_spi1_cs_pins: spi1-cs-pins {
                                        marvell,pins = "mpp59";
                                        marvell,function = "spi1";
        };
 
        /* CON5 */
-       sfp0: sfp {
+       sfp0: sfp-0 {
                compatible = "sff,sfp";
                pinctrl-0 = <&cf_gtr_sfp0_pins>;
                pinctrl-names = "default";