drm/amd/display: Add DCHUBBUB callback to report MALL status

[Why&How]
For enabling automated testing, add a hook to DCHUBBUB interface so that
mall status can be queried by userspace through debugfs. This removes
dependence on requiring a userspace tool like UMR for querying status
for MALL static screen IGT test.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 05c1ad98a1f65148a2c21b02ac558bf67b984aed..1259d6351c50b79d9ac6c229a39d4a314d324c2d 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -37,6 +37,7 @@
 #include "link_hwss.h"
 #include "dc/dc_dmub_srv.h"
 #include "link/protocols/link_dp_capability.h"
+#include "inc/hw/dchubbub.h"
 
 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 #include "amdgpu_dm_psr.h"
@@ -3642,10 +3643,16 @@ DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get,
 static int capabilities_show(struct seq_file *m, void *unused)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
-       struct dc_caps caps = adev->dm.dc->caps;
-       bool mall_supported = caps.mall_size_total;
+       struct dc *dc = adev->dm.dc;
+       bool mall_supported = dc->caps.mall_size_total;
+       unsigned int mall_in_use = false;
+       struct hubbub *hubbub = dc->res_pool->hubbub;
+
+       if (hubbub->funcs->get_mall_en)
+               hubbub->funcs->get_mall_en(hubbub, &mall_in_use);
 
-       seq_printf(m, "mall: %s\n", mall_supported ? "yes" : "no");
+       seq_printf(m, "mall supported: %s, enabled: %s\n",
+                          mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no");
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index adc876156d2e61a71ec5a91927baef60c8d3804e..5ddf2b36986e82732123e1ad031b796deebd2892 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -171,6 +171,7 @@ struct dcn_hubbub_registers {
        uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;
        uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;
        uint32_t DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;
+       uint32_t DCHUBBUB_ARB_MALL_CNTL;
        uint32_t SDPIF_REQUEST_RATE_LIMIT;
        uint32_t DCHUBBUB_SDPIF_CFG0;
        uint32_t DCHUBBUB_SDPIF_CFG1;
@@ -194,7 +195,9 @@ struct dcn_hubbub_registers {
                type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_A;\
                type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B;\
                type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C;\
-               type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D
+               type DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D;\
+               type MALL_PREFETCH_COMPLETE;\
+               type MALL_IN_USE
 
 #define HUBBUB_REG_FIELD_LIST_DCN35(type) \
                type DCHUBBUB_FGCG_REP_DIS

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
index 8bfef6d095b20136abb4b61d20077c21528c9141..88dfc907553d4c1fa4edc9ee74bd6c75c1e9869f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.c
@@ -945,6 +945,17 @@ void hubbub32_force_wm_propagate_to_pipes(struct hubbub *hubbub)
                        DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
 }
 
+void hubbub32_get_mall_en(struct hubbub *hubbub, unsigned int *mall_in_use)
+{
+       struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
+       uint32_t prefetch_complete, mall_en;
+
+       REG_GET_2(DCHUBBUB_ARB_MALL_CNTL, MALL_IN_USE, &mall_en,
+                         MALL_PREFETCH_COMPLETE, &prefetch_complete);
+
+       *mall_in_use = prefetch_complete && mall_en;
+}
+
 void hubbub32_init(struct hubbub *hubbub)
 {
        struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub);
@@ -995,7 +1006,8 @@ static const struct hubbub_funcs hubbub32_funcs = {
        .init_crb = dcn32_init_crb,
        .hubbub_read_state = hubbub2_read_state,
        .force_usr_retraining_allow = hubbub32_force_usr_retraining_allow,
-       .set_request_limit = hubbub32_set_request_limit
+       .set_request_limit = hubbub32_set_request_limit,
+       .get_mall_en = hubbub32_get_mall_en,
 };
 
 void hubbub32_construct(struct dcn20_hubbub *hubbub2,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
index ad33427192c60c34f5a7993718e27dc3f1e545b1..f073839a4b6d2360b628531a8898d40d6fdee0ac 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hubbub.h
@@ -110,7 +110,9 @@
        HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\
        HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\
        HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\
-       HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh)
+       HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh),\
+       HUBBUB_SF(DCHUBBUB_ARB_MALL_CNTL, MALL_PREFETCH_COMPLETE, mask_sh),\
+       HUBBUB_SF(DCHUBBUB_ARB_MALL_CNTL, MALL_IN_USE, mask_sh)
 
 
 
@@ -157,4 +159,6 @@ void hubbub32_construct(struct dcn20_hubbub *hubbub2,
 
 void hubbub32_set_request_limit(struct hubbub *hubbub, int umc_count, int words_per_umc);
 
+void hubbub32_get_mall_en(struct hubbub *hubbub, unsigned int *mall_in_use);
+
 #endif

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
index c76de61029e0c70169b4834a3e9ae1d2d2c374eb..f075982363be21a7b4338a58324c9b06556e66a9 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
@@ -1283,6 +1283,7 @@ bool dcn32_subvp_vblank_admissable(struct dc *dc, struct dc_state *context, int
       SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_B),                         \
       SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_C),                         \
       SR(DCHUBBUB_ARB_FCLK_PSTATE_CHANGE_WATERMARK_D),                         \
+      SR(DCHUBBUB_ARB_MALL_CNTL),                                              \
       SR(DCN_VM_FAULT_ADDR_MSB), SR(DCN_VM_FAULT_ADDR_LSB),                    \
       SR(DCN_VM_FAULT_CNTL), SR(DCN_VM_FAULT_STATUS),                          \
       SR(SDPIF_REQUEST_RATE_LIMIT)                                             \

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index f5677dbb4e7d894c2e60373f1c756618df74d633..cea05843990c52ed4f7e11852547b4565865490d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -193,6 +193,7 @@ struct hubbub_funcs {
        void (*force_usr_retraining_allow)(struct hubbub *hubbub, bool allow);
        void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel);
        void (*dchubbub_init)(struct hubbub *hubbub);
+       void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use);
 };
 
 struct hubbub {