arm64: dts: ti: k3-am65-base-board: Add IPC sub-mailbox nodes for R5Fs

Add the sub-mailbox nodes that are used to communicate between MPU and
the two R5F remote processors present in the MCU domain to the AM654
EVM base board. These sub-mailbox nodes utilize the System Mailbox
clusters 0 and 1. The interrupts associated with the Mailbox Cluster
User interrupt used by the sub-mailbox nodes are also added. The GIC_SPI
interrupt to be used is dynamically allocated and managed by the System
Firmware through the ti-sci-intr irqchip driver. All the remaining
mailbox clusters are currently not used on A53 core, and so are disabled.

The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The Cortex R5F processor
sub-system is assumed to be running in Split mode, so a sub-mailbox node
is used by each of the R5F cores. Only the sub-mailbox node from cluster 0
is used in case of Lockstep mode.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 1102b84f853d71c661a126ec4a01cf42d34a6f2d..5a1f7c4e01c665602a8a4681b9fbdf801dfbb588 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -280,3 +280,61 @@
 &pcie1_ep {
        status = "disabled";
 };
+
+&mailbox0_cluster0 {
+       interrupts = <164 0>;
+
+       mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+               ti,mbox-tx = <1 0 0>;
+               ti,mbox-rx = <0 0 0>;
+       };
+};
+
+&mailbox0_cluster1 {
+       interrupts = <165 0>;
+
+       mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+               ti,mbox-tx = <1 0 0>;
+               ti,mbox-rx = <0 0 0>;
+       };
+};
+
+&mailbox0_cluster2 {
+       status = "disabled";
+};
+
+&mailbox0_cluster3 {
+       status = "disabled";
+};
+
+&mailbox0_cluster4 {
+       status = "disabled";
+};
+
+&mailbox0_cluster5 {
+       status = "disabled";
+};
+
+&mailbox0_cluster6 {
+       status = "disabled";
+};
+
+&mailbox0_cluster7 {
+       status = "disabled";
+};
+
+&mailbox0_cluster8 {
+       status = "disabled";
+};
+
+&mailbox0_cluster9 {
+       status = "disabled";
+};
+
+&mailbox0_cluster10 {
+       status = "disabled";
+};
+
+&mailbox0_cluster11 {
+       status = "disabled";
+};