riscv: dts: starfive: jh7100: Add watchdog node

Add watchdog node for the StarFive JH7100 RISC-V SoC.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 000447482acaa504020b9994c7e2701c8e09eb8d..4218621ea3b92c90a6b8b81bc4015649cc7eda3e 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -238,5 +238,15 @@
                        #size-cells = <0>;
                        status = "disabled";
                };
+
+               watchdog@12480000 {
+                       compatible = "starfive,jh7100-wdt";
+                       reg = <0x0 0x12480000 0x0 0x10000>;
+                       clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
+                                <&clkgen JH7100_CLK_WDT_CORE>;
+                       clock-names = "apb", "core";
+                       resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
+                                <&rstgen JH7100_RSTN_WDT>;
+               };
        };
 };