#include "qapi/error.h"
#include "qemu-common.h"
#include "cpu.h"
+#include "exec/address-spaces.h"
#include "hw/boards.h"
#include "hw/hw.h"
#include "hw/irq.h"
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
-struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
- unsigned long sdram_size,
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *dram,
const char *cpu_type)
{
int i;
qemu_irq dma_irqs[6];
DriveInfo *dinfo;
SysBusDevice *busdev;
+ MemoryRegion *system_memory = get_system_memory();
/* Core */
s->mpu_model = omap310;
s->cpu = ARM_CPU(cpu_create(cpu_type));
- s->sdram_size = sdram_size;
+ s->sdram_size = memory_region_size(dram);
s->sram_size = OMAP15XX_SRAM_SIZE;
s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
omap_clk_init(s);
/* Memory-mapped stuff */
- memory_region_allocate_system_memory(&s->emiff_ram, NULL, "omap1.dram",
- s->sdram_size);
- memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size,
&error_fatal);
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
/* Register SDRAM and SRAM DMA ports for fast transfers. */
- soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->emiff_ram),
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(dram),
OMAP_EMIFF_BASE, s->sdram_size);
soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->imif_ram),
OMAP_IMIF_BASE, s->sram_size);
{
struct omap_mpu_state_s *mpu;
MemoryRegion *address_space = get_system_memory();
+ MemoryRegion *dram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
static uint32_t cs0val = 0x00213090;
flash_size = flash2_size;
}
- mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size,
- machine->cpu_type);
+ memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
+ sx1_binfo.ram_size);
+ memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, dram);
+
+ mpu = omap310_mpu_init(dram, machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size,
MemoryRegion *address_space_mem = get_system_memory();
struct omap_mpu_state_s *mpu;
int flash_size = 0x00800000;
- int sdram_size = palmte_binfo.ram_size;
static uint32_t cs0val = 0xffffffff;
static uint32_t cs1val = 0x0000e1a0;
static uint32_t cs2val = 0x0000e1a0;
static uint32_t cs3val = 0xe1a0e1a0;
int rom_size, rom_loaded = 0;
+ MemoryRegion *dram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *cs = g_new(MemoryRegion, 4);
- mpu = omap310_mpu_init(address_space_mem, sdram_size, machine->cpu_type);
+ memory_region_allocate_system_memory(dram, NULL, "omap1.dram",
+ palmte_binfo.ram_size);
+ memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, dram);
+
+ mpu = omap310_mpu_init(dram, machine->cpu_type);
/* External Flash (EMIFS) */
memory_region_init_ram(flash, NULL, "palmte.flash", flash_size,
MemoryRegion mpui_io_iomem;
MemoryRegion tap_iomem;
MemoryRegion imif_ram;
- MemoryRegion emiff_ram;
MemoryRegion sram;
struct omap_dma_port_if_s {
hwaddr addr);
} port[__omap_dma_port_last];
- unsigned long sdram_size;
+ uint64_t sdram_size;
unsigned long sram_size;
/* MPUI-TIPB peripherals */
};
/* omap1.c */
-struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
- unsigned long sdram_size,
+struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram,
const char *core);
/* omap2.c */