drm/radeon/kms/r600: reduce gpu cache flushing

Only flush the gpu caches before we submit a fence.
This leads to a small performance boost when we take
the extra gpu cache flushes out of the ddx and mesa.
Once this patch is in and the drm version is bumped,
we can remove the flushes from the ddx and drm.

Also, remove the extra cache flushes from the blit
routine.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 9661a469f3bd846033719147e07dce8a804a30ea..7c32a233b23687d393c418a7a7acb0a39d72b31b 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1783,6 +1783,13 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
                          struct radeon_fence *fence)
 {
        /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
+
+       radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
+       radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
+       /* wait for 3D idle clean */
+       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+       radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
+       radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
        /* Emit fence sequence & fire IRQ */
        radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
        radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));

diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index af1c3ca8a4cb0b60cab89149d2c41aaefd6170c6..2d7d16e14f9eb2d1a48298edd316db1fe7885003 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -403,8 +403,6 @@ set_default_state(struct radeon_device *rdev)
        radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
        radeon_ring_write(rdev, dwords);
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
-       radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
        /* SQ config */
        radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
        radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
@@ -581,9 +579,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
        ring_size = num_loops * dwords_per_loop;
        /* set default  + shaders */
        ring_size += 40; /* shaders + def state */
-       ring_size += 7; /* fence emit for VB IB */
+       ring_size += 12; /* fence emit for VB IB */
        ring_size += 5; /* done copy */
-       ring_size += 7; /* fence emit for done copy */
+       ring_size += 12; /* fence emit for done copy */
        r = radeon_ring_lock(rdev, ring_size);
        if (r)
                return r;
@@ -597,13 +595,6 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 {
        int r;
 
-       radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
-       radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
-       /* wait for 3D idle clean */
-       radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
-       radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
-       radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
-
        if (rdev->r600_blit.vb_ib)
                r600_vb_ib_put(rdev);
 

diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c
index d745e815c2e81193bfe9e44c129efc028018985f..a112c59f9d824988a8f0a399380c4041eace903d 100644 (file)
--- a/drivers/gpu/drm/radeon/r600_blit_shaders.c
+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c
@@ -9,11 +9,6 @@ const u32 r6xx_default_state[] =
        0xc0012800,
        0x80000000,
        0x80000000,
-       0xc0004600,
-       0x00000016,
-       0xc0016800,
-       0x00000010,
-       0x00028000,
        0xc0016800,
        0x00000010,
        0x00008000,
@@ -531,11 +526,6 @@ const u32 r7xx_default_state[] =
        0xc0012800,
        0x80000000,
        0x80000000,
-       0xc0004600,
-       0x00000016,
-       0xc0016800,
-       0x00000010,
-       0x00028000,
        0xc0016800,
        0x00000010,
        0x00008000,