lic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);
 
                /* Disable COP interrupts */
-               writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+               writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
 
                /* Disable CPU interrupts */
-               writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+               writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
 
                /* Enable the wakeup sources of ictlr */
                writel_relaxed(lic->ictlr_wake_mask[i], ictlr + ICTLR_CPU_IER_SET);
 
                writel_relaxed(lic->cpu_iep[i],
                               ictlr + ICTLR_CPU_IEP_CLASS);
-               writel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);
+               writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_CPU_IER_CLR);
                writel_relaxed(lic->cpu_ier[i],
                               ictlr + ICTLR_CPU_IER_SET);
                writel_relaxed(lic->cop_iep[i],
                               ictlr + ICTLR_COP_IEP_CLASS);
-               writel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);
+               writel_relaxed(GENMASK(31, 0), ictlr + ICTLR_COP_IER_CLR);
                writel_relaxed(lic->cop_ier[i],
                               ictlr + ICTLR_COP_IER_SET);
        }
                lic->base[i] = base;
 
                /* Disable all interrupts */
-               writel_relaxed(~0UL, base + ICTLR_CPU_IER_CLR);
+               writel_relaxed(GENMASK(31, 0), base + ICTLR_CPU_IER_CLR);
                /* All interrupts target IRQ */
                writel_relaxed(0, base + ICTLR_CPU_IEP_CLASS);