drm/amdgpu: add read amdgpu_gfxoff status in debugfs

 Add interface for SMU12 device, used by UMR.

v2: fix code style

Signed-off-by: Jinzhou.Su <Jinzhou.Su@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index a3fa1560de96c98156b4f2f0e4292053389a8d34..193ffdb957b67f194aaf400dc4cc7d7f23a7b685 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -1073,6 +1073,57 @@ static ssize_t amdgpu_debugfs_gfxoff_write(struct file *f, const char __user *bu
 }
 
 
+/**
+ * amdgpu_debugfs_regs_gfxoff_status - read gfxoff status
+ *
+ * @f: open file handle
+ * @buf: User buffer to store read data in
+ * @size: Number of bytes to read
+ * @pos:  Offset to seek to
+ */
+static ssize_t amdgpu_debugfs_gfxoff_read(struct file *f, char __user *buf,
+                                        size_t size, loff_t *pos)
+{
+       struct amdgpu_device *adev = file_inode(f)->i_private;
+       ssize_t result = 0;
+       int r;
+
+       if (size & 0x3 || *pos & 0x3)
+               return -EINVAL;
+
+       r = pm_runtime_get_sync(adev->ddev->dev);
+       if (r < 0)
+               return r;
+
+       while (size) {
+               uint32_t value;
+
+               r = amdgpu_get_gfx_off_status(adev, &value);
+               if (r) {
+                       pm_runtime_mark_last_busy(adev->ddev->dev);
+                       pm_runtime_put_autosuspend(adev->ddev->dev);
+                       return r;
+               }
+
+               r = put_user(value, (uint32_t *)buf);
+               if (r) {
+                       pm_runtime_mark_last_busy(adev->ddev->dev);
+                       pm_runtime_put_autosuspend(adev->ddev->dev);
+                       return r;
+               }
+
+               result += 4;
+               buf += 4;
+               *pos += 4;
+               size -= 4;
+       }
+
+       pm_runtime_mark_last_busy(adev->ddev->dev);
+       pm_runtime_put_autosuspend(adev->ddev->dev);
+
+       return result;
+}
+
 static const struct file_operations amdgpu_debugfs_regs_fops = {
        .owner = THIS_MODULE,
        .read = amdgpu_debugfs_regs_read,
@@ -1123,7 +1174,9 @@ static const struct file_operations amdgpu_debugfs_gpr_fops = {
 
 static const struct file_operations amdgpu_debugfs_gfxoff_fops = {
        .owner = THIS_MODULE,
+       .read = amdgpu_debugfs_gfxoff_read,
        .write = amdgpu_debugfs_gfxoff_write,
+       .llseek = default_llseek
 };
 
 static const struct file_operations *debugfs_regs[] = {

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index d612033a23ac638d8b6e0a56cdb48cb63eeb62a8..78d37f92c7be53eb82f006f4d0da95519d3dcecf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -578,6 +578,20 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable)
        mutex_unlock(&adev->gfx.gfx_off_mutex);
 }
 
+int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value)
+{
+
+       int r = 0;
+
+       mutex_lock(&adev->gfx.gfx_off_mutex);
+
+       r = smu_get_status_gfxoff(adev, value);
+
+       mutex_unlock(&adev->gfx.gfx_off_mutex);
+
+       return r;
+}
+
 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev)
 {
        int r;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 50be8e3a443b634c0486c31b1302f79a35a8e582..1e7a2b0997c56a58b6c9426db48ccc17f4718433 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -378,6 +378,7 @@ void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit,
 bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
                                    int pipe, int queue);
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
+int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev);
 void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 03125c8a2145eea85dcf92446db0408881f575ab..3b817079dac03f54cd5da8026cda7c280314f77c 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -239,6 +239,19 @@ int smu_get_smc_version(struct smu_context *smu, uint32_t *if_version, uint32_t
        return ret;
 }
 
+int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
+{
+       int ret = 0;
+       struct smu_context *smu = &adev->smu;
+
+       if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
+               *value = smu_get_gfx_off_status(smu);
+       else
+               ret = -EINVAL;
+
+       return ret;
+}
+
 int smu_set_soft_freq_range(struct smu_context *smu,
                            enum smu_clk_type clk_type,
                            uint32_t min,

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 70181ba7ee0c0da910e7d7ec6dd9ca366f91437d..8333fafbe278db1abd162413325de92f2739f47d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -555,6 +555,7 @@ struct pptable_funcs {
        int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed);
        int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
        int (*gfx_off_control)(struct smu_context *smu, bool enable);
+       uint32_t (*get_gfx_off_status)(struct smu_context *smu);
        int (*register_irq_handler)(struct smu_context *smu);
        int (*set_azalia_d3_pme)(struct smu_context *smu);
        int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct pp_smu_nv_clock_table *max_clocks);
@@ -755,4 +756,6 @@ int smu_get_uclk_dpm_states(struct smu_context *smu,
 int smu_get_dpm_clock_table(struct smu_context *smu,
                            struct dpm_clocks *clock_table);
 
+int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
+
 #endif

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 79cadc2df0d54161946934451f442beab852cbd8..a268df85295f510f1c8c5fc3a11076eadd0f7f01 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -1087,6 +1087,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
        .send_smc_msg_with_param = smu_v12_0_send_msg_with_param,
        .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
        .gfx_off_control = smu_v12_0_gfx_off_control,
+       .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
        .init_smc_tables = smu_v12_0_init_smc_tables,
        .fini_smc_tables = smu_v12_0_fini_smc_tables,
        .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,

diff --git a/drivers/gpu/drm/amd/powerplay/smu_internal.h b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index afb3ef874fc5d73fb0353fb7290847f36fc45f2e..ab73a3fd634c61979d45d56c29a2fcce9dd04b80 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -44,6 +44,7 @@
 #define smu_set_tool_table_location(smu)                               smu_ppt_funcs(set_tool_table_location, 0, smu)
 #define smu_notify_memory_pool_location(smu)                           smu_ppt_funcs(notify_memory_pool_location, 0, smu)
 #define smu_gfx_off_control(smu, enable)                               smu_ppt_funcs(gfx_off_control, 0, smu, enable)
+#define smu_get_gfx_off_status(smu)                                            smu_ppt_funcs(get_gfx_off_status, 0, smu)
 #define smu_set_last_dcef_min_deep_sleep_clk(smu)                      smu_ppt_funcs(set_last_dcef_min_deep_sleep_clk, 0, smu)
 #define smu_system_features_control(smu, en)                           smu_ppt_funcs(system_features_control, 0, smu, en)
 #define smu_init_max_sustainable_clocks(smu)                           smu_ppt_funcs(init_max_sustainable_clocks, 0, smu)