drm/i915/tgl: move DP_TP_* to transcoder

Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This adds the new register addresses and changes all
the callers to use the register saved in intel_dp->regs.*. This is
filled out when preparing to enable the port so we take into account if
we should use the transcoder or the port.

v2: reimplement by stashing the registers we want to access under
intel_dp->reg. Now they are initialized when enabling the port.
Ville suggested to store the transcoder to be used exclusively
by TGL+. After implementing I thought just storing the register directly
made it cleaner.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190904213419.27547-5-jose.souza@intel.com
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ec132cd6add8845bcb3fdb56c78d6372bbd84868..3e6394139964dc3f58636a2a4419c4bc116b4a2a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3167,17 +3167,18 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder,
                                 const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       enum port port = encoder->port;
+       struct intel_dp *intel_dp;
        u32 val;
 
        if (!crtc_state->fec_enable)
                return;
 
-       val = I915_READ(DP_TP_CTL(port));
+       intel_dp = enc_to_intel_dp(&encoder->base);
+       val = I915_READ(intel_dp->regs.dp_tp_ctl);
        val |= DP_TP_CTL_FEC_ENABLE;
-       I915_WRITE(DP_TP_CTL(port), val);
+       I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
 
-       if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+       if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
                                  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
                DRM_ERROR("Timed out waiting for FEC Enable Status\n");
 }
@@ -3186,16 +3187,17 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
                                        const struct intel_crtc_state *crtc_state)
 {
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       enum port port = encoder->port;
+       struct intel_dp *intel_dp;
        u32 val;
 
        if (!crtc_state->fec_enable)
                return;
 
-       val = I915_READ(DP_TP_CTL(port));
+       intel_dp = enc_to_intel_dp(&encoder->base);
+       val = I915_READ(intel_dp->regs.dp_tp_ctl);
        val &= ~DP_TP_CTL_FEC_ENABLE;
-       I915_WRITE(DP_TP_CTL(port), val);
-       POSTING_READ(DP_TP_CTL(port));
+       I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+       POSTING_READ(intel_dp->regs.dp_tp_ctl);
 }
 
 static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
@@ -3208,10 +3210,14 @@ static void tgl_ddi_pre_enable_dp(struct intel_encoder *encoder,
        struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
        bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
        int level = intel_ddi_dp_level(intel_dp);
+       enum transcoder transcoder = crtc_state->cpu_transcoder;
 
        intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
                                 crtc_state->lane_count, is_mst);
 
+       intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
+       intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
+
        /* 1.a got on intel_atomic_commit_tail() */
 
        /* 2. */
@@ -3300,6 +3306,9 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
        intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
                                 crtc_state->lane_count, is_mst);
 
+       intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
+       intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
+
        intel_edp_panel_on(intel_dp);
 
        intel_ddi_clk_select(encoder, crtc_state);
@@ -3466,10 +3475,12 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
        }
 
        if (intel_crtc_has_dp_encoder(crtc_state)) {
-               val = I915_READ(DP_TP_CTL(port));
+               struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+
+               val = I915_READ(intel_dp->regs.dp_tp_ctl);
                val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
                val |= DP_TP_CTL_LINK_TRAIN_PAT1;
-               I915_WRITE(DP_TP_CTL(port), val);
+               I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
        }
 
        /* Disable FEC in DP Sink */
@@ -3898,7 +3909,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
        u32 val;
        bool wait = false;
 
-       if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
+       if (I915_READ(intel_dp->regs.dp_tp_ctl) & DP_TP_CTL_ENABLE) {
                val = I915_READ(DDI_BUF_CTL(port));
                if (val & DDI_BUF_CTL_ENABLE) {
                        val &= ~DDI_BUF_CTL_ENABLE;
@@ -3906,11 +3917,11 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
                        wait = true;
                }
 
-               val = I915_READ(DP_TP_CTL(port));
+               val = I915_READ(intel_dp->regs.dp_tp_ctl);
                val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
                val |= DP_TP_CTL_LINK_TRAIN_PAT1;
-               I915_WRITE(DP_TP_CTL(port), val);
-               POSTING_READ(DP_TP_CTL(port));
+               I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+               POSTING_READ(intel_dp->regs.dp_tp_ctl);
 
                if (wait)
                        intel_wait_ddi_buf_idle(dev_priv, port);
@@ -3925,8 +3936,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                        val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
        }
-       I915_WRITE(DP_TP_CTL(port), val);
-       POSTING_READ(DP_TP_CTL(port));
+       I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
+       POSTING_READ(intel_dp->regs.dp_tp_ctl);
 
        intel_dp->DP |= DDI_BUF_CTL_ENABLE;
        I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 61277a87dbe7aaae5d70f58726b7b0b245ad5682..d5cc4b810d9ef4d352b97b6ab5d8079643fe58fd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1218,6 +1218,15 @@ struct intel_dp {
        bool can_mst; /* this port supports mst */
        bool is_mst;
        int active_mst_links;
+
+       /*
+        * DP_TP_* registers may be either on port or transcoder register space.
+        */
+       struct {
+               i915_reg_t dp_tp_ctl;
+               i915_reg_t dp_tp_status;
+       } regs;
+
        /* connector directly attached - won't be use for modeset in mst world */
        struct intel_connector *attached_connector;
 

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 4e3e696e7fc845f7564eb323a7d6a4199540795e..f06fbca5cb3ea48427a5feebab084eb20a3c31e0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2297,6 +2297,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
                                 intel_crtc_has_type(pipe_config,
                                                     INTEL_OUTPUT_DP_MST));
 
+       intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
+       intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
+
        /*
         * There are four kinds of DP registers:
         *
@@ -3253,7 +3256,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
                              dp_train_pat & train_pat_mask);
 
        if (HAS_DDI(dev_priv)) {
-               u32 temp = I915_READ(DP_TP_CTL(port));
+               u32 temp = I915_READ(intel_dp->regs.dp_tp_ctl);
 
                if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
                        temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
@@ -3279,7 +3282,7 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
                        temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
                        break;
                }
-               I915_WRITE(DP_TP_CTL(port), temp);
+               I915_WRITE(intel_dp->regs.dp_tp_ctl, temp);
 
        } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
                   (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
@@ -3980,10 +3983,10 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
        if (!HAS_DDI(dev_priv))
                return;
 
-       val = I915_READ(DP_TP_CTL(port));
+       val = I915_READ(intel_dp->regs.dp_tp_ctl);
        val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
        val |= DP_TP_CTL_LINK_TRAIN_IDLE;
-       I915_WRITE(DP_TP_CTL(port), val);
+       I915_WRITE(intel_dp->regs.dp_tp_ctl, val);
 
        /*
         * Until TGL on PORT_A we can have only eDP in SST mode. There the only
@@ -3995,7 +3998,7 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
        if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
                return;
 
-       if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+       if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
                                  DP_TP_STATUS_IDLE_DONE, 1))
                DRM_ERROR("Timed out waiting for DP idle patterns\n");
 }

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 37366f81255b454bf6a863ea18461e3035113a21..3f9cdbaab95e66f138bbfae039d5117718582fcd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -295,7 +295,6 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
        struct intel_digital_port *intel_dig_port = intel_mst->primary;
        struct intel_dp *intel_dp = &intel_dig_port->dp;
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       enum port port = intel_dig_port->base.port;
        struct intel_connector *connector =
                to_intel_connector(conn_state->connector);
        int ret;
@@ -326,8 +325,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
                DRM_ERROR("failed to allocate vcpi\n");
 
        intel_dp->active_mst_links++;
-       temp = I915_READ(DP_TP_STATUS(port));
-       I915_WRITE(DP_TP_STATUS(port), temp);
+       temp = I915_READ(intel_dp->regs.dp_tp_status);
+       I915_WRITE(intel_dp->regs.dp_tp_status, temp);
 
        ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr);
 
@@ -342,11 +341,10 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder,
        struct intel_digital_port *intel_dig_port = intel_mst->primary;
        struct intel_dp *intel_dp = &intel_dig_port->dp;
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
-       enum port port = intel_dig_port->base.port;
 
        DRM_DEBUG_KMS("active links %d\n", intel_dp->active_mst_links);
 
-       if (intel_de_wait_for_set(dev_priv, DP_TP_STATUS(port),
+       if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
                                  DP_TP_STATUS_ACT_SENT, 1))
                DRM_ERROR("Timed out waiting for ACT sent\n");
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index de9e679e90bb51e60105e516d655d9c6e6350a7a..006cffd56be27b6a911bc2c4a44e2a048ec399c1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9546,7 +9546,9 @@ enum skl_power_gate {
 /* DisplayPort Transport Control */
 #define _DP_TP_CTL_A                   0x64040
 #define _DP_TP_CTL_B                   0x64140
+#define _TGL_DP_TP_CTL_A               0x60540
 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B)
+#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A)
 #define  DP_TP_CTL_ENABLE                      (1 << 31)
 #define  DP_TP_CTL_FEC_ENABLE                  (1 << 30)
 #define  DP_TP_CTL_MODE_SST                    (0 << 27)
@@ -9566,7 +9568,9 @@ enum skl_power_gate {
 /* DisplayPort Transport Status */
 #define _DP_TP_STATUS_A                        0x64044
 #define _DP_TP_STATUS_B                        0x64144
+#define _TGL_DP_TP_STATUS_A            0x60544
 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B)
+#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A)
 #define  DP_TP_STATUS_FEC_ENABLE_LIVE          (1 << 28)
 #define  DP_TP_STATUS_IDLE_DONE                        (1 << 25)
 #define  DP_TP_STATUS_ACT_SENT                 (1 << 24)