arm64: dts: qcom: sa8775p: add uart5 and uart9 nodes

Add remaining uart5 and uart9 nodes for UART bus present on sa8775p
SoC.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-5-quic_shazhuss@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index df7e0f8f782c9957e59113949ff86aa742b2bdec..0385fc810d4cb9f84a7f1a8b175d4eac7e634f41 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -1063,6 +1063,21 @@
                                power-domains = <&rpmhpd SA8775P_CX>;
                                status = "disabled";
                        };
+
+                       uart5: serial@994000 {
+                               compatible = "qcom,geni-uart";
+                               reg = <0x0 0x994000 0x0 0x4000>;
+                               interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+                               clock-names = "se";
+                               interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
+                                                &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
+                                               <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+                                                &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
+                               interconnect-names = "qup-core", "qup-config";
+                               power-domains = <&rpmhpd SA8775P_CX>;
+                               status = "disabled";
+                       };
                };
 
                qupv3_id_1: geniqup@ac0000 {
@@ -1203,6 +1218,21 @@
                                status = "disabled";
                        };
 
+                       uart9: serial@a88000 {
+                               compatible = "qcom,geni-uart";
+                               reg = <0x0 0xa88000 0x0 0x4000>;
+                               interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+                               clock-names = "se";
+                               interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
+                                                &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
+                                               <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+                                                &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
+                               interconnect-names = "qup-core", "qup-config";
+                               power-domains = <&rpmhpd SA8775P_CX>;
+                               status = "disabled";
+                       };
+
                        i2c10: i2c@a8c000 {
                                compatible = "qcom,geni-i2c";
                                reg = <0x0 0xa8c000 0x0 0x4000>;