drm/amd/swsmu: add if condition for smu v14.0.1

smu v14.0.1 re-used smu v14.0.0

Signed-off-by: Li Ma <li.ma@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
index 3bc9662fbd283c08e234c2334c721aa82ebb44b6..7d2055b9d19f319f613278a82d76a8634e9b936e 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c
@@ -136,7 +136,8 @@ int smu_v14_0_load_microcode(struct smu_context *smu)
                    1 & ~MP1_SMN_PUB_CTRL__LX3_RESET_MASK);
 
        for (i = 0; i < adev->usec_timeout; i++) {
-               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
+               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+                       amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
                        mp1_fw_flags = RREG32_PCIE(MP1_Public |
                                                   (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
                else
@@ -209,7 +210,8 @@ int smu_v14_0_check_fw_status(struct smu_context *smu)
        struct amdgpu_device *adev = smu->adev;
        uint32_t mp1_fw_flags;
 
-       if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0))
+       if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+               amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1))
                mp1_fw_flags = RREG32_PCIE(MP1_Public |
                                           (smnMP1_FIRMWARE_FLAGS_14_0_0 & 0xffffffff));
        else
@@ -856,7 +858,8 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
                // TODO
 
                /* For MP1 SW irqs */
-               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
+               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+                       amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
                        val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0);
                        val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
                        WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0, val);
@@ -872,7 +875,8 @@ static int smu_v14_0_set_irq_state(struct amdgpu_device *adev,
                // TODO
 
                /* For MP1 SW irqs */
-               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0)) {
+               if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 0) ||
+                       amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(14, 0, 1)) {
                        val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_mp1_14_0_0);
                        val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
                        val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);