/* set of registers with offsets different per-PHY */
 enum qphy_reg_layout {
-       /* Common block control registers */
-       QPHY_COM_SW_RESET,
-       QPHY_COM_POWER_DOWN_CONTROL,
-       QPHY_COM_START_CONTROL,
-       QPHY_COM_PCS_READY_STATUS,
        /* PCS registers */
        QPHY_SW_RESET,
        QPHY_START_CTRL,
 };
 
 static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
-       [QPHY_COM_SW_RESET]             = 0x400,
-       [QPHY_COM_POWER_DOWN_CONTROL]   = 0x404,
-       [QPHY_COM_START_CONTROL]        = 0x408,
-       [QPHY_COM_PCS_READY_STATUS]     = 0x448,
        [QPHY_SW_RESET]                 = 0x00,
        [QPHY_START_CTRL]               = 0x08,
        [QPHY_PCS_STATUS]               = 0x174,