drm/amd/display: Add DCN35 CORE
authorQingqing Zhuo <Qingqing.Zhuo@amd.com>
Thu, 3 Aug 2023 06:30:59 +0000 (02:30 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 30 Aug 2023 19:51:16 +0000 (15:51 -0400)
[Why & How]
Add DCN35 support in dc_resource.c.

Signed-off-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/core/dc_resource.c

index 30424ba7761d21473ccee8aa6f42dd628d138a36..c929003825f4641184393bb320c2f7ea59caf6cd 100644 (file)
@@ -70,6 +70,7 @@
 #include "dcn316/dcn316_resource.h"
 #include "../dcn32/dcn32_resource.h"
 #include "../dcn321/dcn321_resource.h"
+#include "dcn35/dcn35_resource.h"
 
 #define VISUAL_CONFIRM_BASE_DEFAULT 3
 #define VISUAL_CONFIRM_BASE_MIN 1
@@ -186,6 +187,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
        case AMDGPU_FAMILY_GC_11_0_1:
                dc_version = DCN_VERSION_3_14;
                break;
+       case AMDGPU_FAMILY_GC_11_5_0:
+               dc_version = DCN_VERSION_3_5;
+               break;
        default:
                dc_version = DCE_VERSION_UNKNOWN;
                break;
@@ -290,6 +294,9 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
        case DCN_VERSION_3_21:
                res_pool = dcn321_create_resource_pool(init_data, dc);
                break;
+       case DCN_VERSION_3_5:
+               res_pool = dcn35_create_resource_pool(init_data, dc);
+               break;
 #endif /* CONFIG_DRM_AMD_DC_FP */
        default:
                break;