drm/i915: Add Wa_14015150844

Disables Atomic-chaining of Typed Writes.

BSpec: 54040
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230901045700.2553994-1-shekhar.chauhan@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 0e4c638fcbbf018b6f3fd25273f774450696ef0a..a00ff51c681d5d5fc2154b24ec1d094e807e305b 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1218,6 +1218,8 @@
 
 #define XEHP_HDC_CHICKEN0                      MCR_REG(0xe5f0)
 #define   LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK       REG_GENMASK(13, 11)
+#define   DIS_ATOMIC_CHAINING_TYPED_WRITES     REG_BIT(3)
+
 #define ICL_HDC_MODE                           MCR_REG(0xe5f4)
 
 #define EU_PERF_CNTL2                          PERF_REG(0xe658)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 12ac218afb2a3456af56b9f0d19f7d27f5cb25ce..e950efc75983ef36559e4510a2aaf7f22a2113d0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -2326,6 +2326,14 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
                                  LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK);
        }
 
+       if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) ||
+           IS_DG2(i915)) {
+               /* Wa_14015150844 */
+               wa_mcr_add(wal, XEHP_HDC_CHICKEN0, 0,
+                          _MASKED_BIT_ENABLE(DIS_ATOMIC_CHAINING_TYPED_WRITES),
+                          0, true);
+       }
+
        if (IS_DG2_G11(i915) || IS_DG2_G10(i915)) {
                /* Wa_22014600077:dg2 */
                wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0,