riscv: dts: starfive: fix jh7110 qspi sort order

Emil pointed out that "13010000 sorts after 12070000". Reshuffle the
entries to be in-order.

Reported-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 9aa563898868e414d4bd32f915a912e72e1a6ccf..e85464c328d07e4307cc6f7e30a889685a6d9c36 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -676,25 +676,6 @@
                        status = "disabled";
                };
 
-               qspi: spi@13010000 {
-                       compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
-                       reg = <0x0 0x13010000 0x0 0x10000>,
-                             <0x0 0x21000000 0x0 0x400000>;
-                       interrupts = <25>;
-                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
-                                <&syscrg JH7110_SYSCLK_QSPI_AHB>,
-                                <&syscrg JH7110_SYSCLK_QSPI_APB>;
-                       clock-names = "ref", "ahb", "apb";
-                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
-                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
-                                <&syscrg JH7110_SYSRST_QSPI_REF>;
-                       reset-names = "qspi", "qspi-ocp", "rstc_ref";
-                       cdns,fifo-depth = <256>;
-                       cdns,fifo-width = <4>;
-                       cdns,trigger-address = <0x0>;
-                       status = "disabled";
-               };
-
                spi3: spi@12070000 {
                        compatible = "arm,pl022", "arm,primecell";
                        reg = <0x0 0x12070000 0x0 0x10000>;
@@ -767,6 +748,25 @@
                        #thermal-sensor-cells = <0>;
                };
 
+               qspi: spi@13010000 {
+                       compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
+                       reg = <0x0 0x13010000 0x0 0x10000>,
+                             <0x0 0x21000000 0x0 0x400000>;
+                       interrupts = <25>;
+                       clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
+                                <&syscrg JH7110_SYSCLK_QSPI_AHB>,
+                                <&syscrg JH7110_SYSCLK_QSPI_APB>;
+                       clock-names = "ref", "ahb", "apb";
+                       resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
+                                <&syscrg JH7110_SYSRST_QSPI_AHB>,
+                                <&syscrg JH7110_SYSRST_QSPI_REF>;
+                       reset-names = "qspi", "qspi-ocp", "rstc_ref";
+                       cdns,fifo-depth = <256>;
+                       cdns,fifo-width = <4>;
+                       cdns,trigger-address = <0x0>;
+                       status = "disabled";
+               };
+
                syscrg: clock-controller@13020000 {
                        compatible = "starfive,jh7110-syscrg";
                        reg = <0x0 0x13020000 0x0 0x10000>;