}
        }
 
-       if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->pin_count)
+       if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count)
                amdgpu_bo_fence(bo,
                                &avm->process_info->eviction_fence->base,
                                true);
         * required.
         */
        if (mem->mapped_to_gpu_memory == 0 &&
-           !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && !mem->bo->pin_count)
+           !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) &&
+           !mem->bo->tbo.pin_count)
                amdgpu_amdkfd_remove_eviction_fence(mem->bo,
                                                process_info->eviction_fence);
 
 
        uint32_t domain;
        int r;
 
-       if (bo->pin_count)
+       if (bo->tbo.pin_count)
                return 0;
 
        /* Don't move this buffer if we have depleted our allowance
 
        /* unpin of the old buffer */
        r = amdgpu_bo_reserve(work->old_abo, true);
        if (likely(r == 0)) {
-               r = amdgpu_bo_unpin(work->old_abo);
-               if (unlikely(r != 0)) {
-                       DRM_ERROR("failed to unpin buffer after flip\n");
-               }
+               amdgpu_bo_unpin(work->old_abo);
                amdgpu_bo_unreserve(work->old_abo);
        } else
                DRM_ERROR("failed to reserve buffer after flip\n");
        }
 unpin:
        if (!adev->enable_virtual_display)
-               if (unlikely(amdgpu_bo_unpin(new_abo) != 0))
-                       DRM_ERROR("failed to unpin new abo in error path\n");
+               amdgpu_bo_unpin(new_abo);
 
 unreserve:
        amdgpu_bo_unreserve(new_abo);
 
        struct sg_table *sgt;
        long r;
 
-       if (!bo->pin_count) {
+       if (!bo->tbo.pin_count) {
                /* move buffer into GTT or VRAM */
                struct ttm_operation_ctx ctx = { false, false };
                unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
        if (unlikely(ret != 0))
                return ret;
 
-       if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
+       if (!bo->tbo.pin_count &&
+           (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
                amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
                ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
        }
 
        seq_printf(m, "\t0x%08x: %12ld byte %s",
                   id, amdgpu_bo_size(bo), placement);
 
-       pin_count = READ_ONCE(bo->pin_count);
+       pin_count = READ_ONCE(bo->tbo.pin_count);
        if (pin_count)
                seq_printf(m, " pin count %d", pin_count);
 
 
        struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
        struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
 
-       if (bo->pin_count > 0)
+       if (bo->tbo.pin_count > 0)
                amdgpu_bo_subtract_pin_size(bo);
 
        amdgpu_bo_kunmap(bo);
        uint32_t domain;
        int r;
 
-       if (bo->pin_count)
+       if (bo->tbo.pin_count)
                return 0;
 
        domain = bo->preferred_domains;
         */
        domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
 
-       if (bo->pin_count) {
+       if (bo->tbo.pin_count) {
                uint32_t mem_type = bo->tbo.mem.mem_type;
 
                if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
                        return -EINVAL;
 
-               bo->pin_count++;
+               ttm_bo_pin(&bo->tbo);
 
                if (max_offset != 0) {
                        u64 domain_start = amdgpu_ttm_domain_start(adev,
                if (!bo->placements[i].lpfn ||
                    (lpfn && lpfn < bo->placements[i].lpfn))
                        bo->placements[i].lpfn = lpfn;
-               bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
        }
 
        r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
                goto error;
        }
 
-       bo->pin_count = 1;
+       ttm_bo_pin(&bo->tbo);
 
        domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
        if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
  * Returns:
  * 0 for success or a negative error code on failure.
  */
-int amdgpu_bo_unpin(struct amdgpu_bo *bo)
+void amdgpu_bo_unpin(struct amdgpu_bo *bo)
 {
-       struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-       struct ttm_operation_ctx ctx = { false, false };
-       int r, i;
-
-       if (WARN_ON_ONCE(!bo->pin_count)) {
-               dev_warn(adev->dev, "%p unpin not necessary\n", bo);
-               return 0;
-       }
-       bo->pin_count--;
-       if (bo->pin_count)
-               return 0;
+       ttm_bo_unpin(&bo->tbo);
+       if (bo->tbo.pin_count)
+               return;
 
        amdgpu_bo_subtract_pin_size(bo);
 
        if (bo->tbo.base.import_attach)
                dma_buf_unpin(bo->tbo.base.import_attach);
-
-       for (i = 0; i < bo->placement.num_placement; i++) {
-               bo->placements[i].lpfn = 0;
-               bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
-       }
-       r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
-       if (unlikely(r))
-               dev_err(adev->dev, "%p validate failed for unpin\n", bo);
-
-       return r;
 }
 
 /**
                return 0;
 
        /* Can't move a pinned BO to visible VRAM */
-       if (abo->pin_count > 0)
+       if (abo->tbo.pin_count > 0)
                return -EINVAL;
 
        /* hurrah the memory is not visible ! */
 {
        WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
        WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
-                    !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel);
+                    !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel);
        WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
        WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
                     !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
 
        struct ttm_buffer_object        tbo;
        struct ttm_bo_kmap_obj          kmap;
        u64                             flags;
-       unsigned                        pin_count;
        u64                             tiling_flags;
        u64                             metadata_flags;
        void                            *metadata;
 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain);
 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
                             u64 min_offset, u64 max_offset);
-int amdgpu_bo_unpin(struct amdgpu_bo *bo);
+void amdgpu_bo_unpin(struct amdgpu_bo *bo);
 int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
 int amdgpu_bo_init(struct amdgpu_device *adev);
 int amdgpu_bo_late_init(struct amdgpu_device *adev);
 
 
        /* Can't move a pinned BO */
        abo = ttm_to_amdgpu_bo(bo);
-       if (WARN_ON_ONCE(abo->pin_count > 0))
+       if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
                return -EINVAL;
 
        adev = amdgpu_ttm_adev(bo->bdev);
 
        if (!amdgpu_bo_is_amdgpu_bo(bo))
                return;
 
-       if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
+       if (bo->pin_count)
                return;
 
        abo = ttm_to_amdgpu_bo(bo);