clk: qcom: mmcc-msm8974: remove ocmemcx_ahb_clk
authorLuca Weiss <luca@z3ntu.xyz>
Sat, 2 Sep 2023 17:34:23 +0000 (19:34 +0200)
committerBjorn Andersson <andersson@kernel.org>
Wed, 20 Sep 2023 14:07:34 +0000 (07:07 -0700)
According to a commit in the 3.4 vendor kernel sources[0] the
ocmemcx_ahb_clk clock "is controlled by RPM and should not be touched by
APPS.".

[0] https://git.codelinaro.org/clo/la/kernel/msm/-/commit/37df5f2d91b4d5768b37fcaacaeea958dd683ebc

And indeed, when using MDSS+GPU+OCMEM on MSM8226 and not using
clk_ignore_unused, when Linux tries to disable the clock the device
crashes and reboots.

And since there's also no evidence of this clock in msm8974 vendor
kernel sources, remove the clock for msm8226 and msm8974.

Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)")
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230902-msm8226-ocmemcx_ahb_clk-remove-v1-1-8124dbde83b9@z3ntu.xyz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
drivers/clk/qcom/mmcc-msm8974.c
include/dt-bindings/clock/qcom,mmcc-msm8974.h

index 1f3bd302fe6ed4b7540a380723a39d56f2636570..a31f6cf0c4e0cef1a1e2ce31bc28ccedd3394219 100644 (file)
@@ -2170,22 +2170,6 @@ static struct clk_branch mmss_s0_axi_clk = {
        },
 };
 
-static struct clk_branch ocmemcx_ahb_clk = {
-       .halt_reg = 0x405c,
-       .clkr = {
-               .enable_reg = 0x405c,
-               .enable_mask = BIT(0),
-               .hw.init = &(struct clk_init_data){
-                       .name = "ocmemcx_ahb_clk",
-                       .parent_hws = (const struct clk_hw*[]){
-                               &mmss_ahb_clk_src.clkr.hw
-                       },
-                       .num_parents = 1,
-                       .ops = &clk_branch2_ops,
-               },
-       },
-};
-
 static struct clk_branch ocmemcx_ocmemnoc_clk = {
        .halt_reg = 0x4058,
        .clkr = {
@@ -2503,7 +2487,6 @@ static struct clk_regmap *mmcc_msm8226_clocks[] = {
        [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
        [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
        [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
-       [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
        [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
        [OXILICX_AHB_CLK] = &oxilicx_ahb_clk.clkr,
        [OXILICX_AXI_CLK] = &oxilicx_axi_clk.clkr,
@@ -2660,7 +2643,6 @@ static struct clk_regmap *mmcc_msm8974_clocks[] = {
        [MMSS_MMSSNOC_BTO_AHB_CLK] = &mmss_mmssnoc_bto_ahb_clk.clkr,
        [MMSS_MMSSNOC_AXI_CLK] = &mmss_mmssnoc_axi_clk.clkr,
        [MMSS_S0_AXI_CLK] = &mmss_s0_axi_clk.clkr,
-       [OCMEMCX_AHB_CLK] = &ocmemcx_ahb_clk.clkr,
        [OCMEMCX_OCMEMNOC_CLK] = &ocmemcx_ocmemnoc_clk.clkr,
        [OCMEMNOC_CLK] = &ocmemnoc_clk.clkr,
        [OXILI_GFX3D_CLK] = &oxili_gfx3d_clk.clkr,
index a62cb0629a7a15091d13a3757433e02451e76ff4..743ee60632eb8aea0fa5347da142ebf22d205bc4 100644 (file)
 #define MMSS_MMSSNOC_BTO_AHB_CLK                       112
 #define MMSS_MMSSNOC_AXI_CLK                           113
 #define MMSS_S0_AXI_CLK                                        114
-#define OCMEMCX_AHB_CLK                                        115
 #define OCMEMCX_OCMEMNOC_CLK                           116
 #define OXILI_OCMEMGX_CLK                              117
 #define OCMEMNOC_CLK                                   118