return (has_vhe() && cpus_have_final_cap(ARM64_HAS_ECV_CNTPOFF));
}
+static int nr_timers(struct kvm_vcpu *vcpu)
+{
+ return NR_KVM_TIMERS;
+}
+
u32 timer_get_ctl(struct arch_timer_context *ctxt)
{
struct kvm_vcpu *vcpu = ctxt->vcpu;
u64 min_delta = ULLONG_MAX;
int i;
- for (i = 0; i < NR_KVM_TIMERS; i++) {
+ for (i = 0; i < nr_timers(vcpu); i++) {
struct arch_timer_context *ctx = &vcpu->arch.timer_cpu.timers[i];
WARN(ctx->loaded, "timer %d loaded\n", i);
* resets the timer to be disabled and unmasked and is compliant with
* the ARMv7 architecture.
*/
- for (int i = 0; i < NR_KVM_TIMERS; i++)
+ for (int i = 0; i < nr_timers(vcpu); i++)
timer_set_ctl(vcpu_get_timer(vcpu, i), 0);
if (timer->enabled) {
- for (int i = 0; i < NR_KVM_TIMERS; i++)
+ for (int i = 0; i < nr_timers(vcpu); i++)
kvm_timer_update_irq(vcpu, false,
vcpu_get_timer(vcpu, i));
mutex_lock(&vcpu->kvm->arch.timer_data.lock);
- for (int i = 0; i < NR_KVM_TIMERS; i++) {
+ for (int i = 0; i < nr_timers(vcpu); i++) {
struct arch_timer_context *ctx;
int irq;
ppis |= BIT(irq);
}
- valid = hweight32(ppis) == NR_KVM_TIMERS;
+ valid = hweight32(ppis) == nr_timers(vcpu);
if (valid)
set_bit(KVM_ARCH_FLAG_TIMER_PPIS_IMMUTABLE, &vcpu->kvm->arch.flags);
if (WARN(!vcpu, "No vcpu context!\n"))
return false;
- for (int i = 0; i < NR_KVM_TIMERS; i++) {
+ for (int i = 0; i < nr_timers(vcpu); i++) {
struct arch_timer_context *ctx;
ctx = vcpu_get_timer(vcpu, i);