ARM: dts: owl-s500: Add RoseapplePi

Add a Device Tree for the RoseapplePi SBC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Peter Korsgaard <peter@korsgaard.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5d5e370af290e646dd4b8bc536cfa4d7daa5f7de..b7854859e6b41c215cdc874ed989ea9002353a26 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -869,6 +869,7 @@ dtb-$(CONFIG_ARCH_ACTIONS) += \
        owl-s500-cubieboard6.dtb \
        owl-s500-guitar-bb-rev-b.dtb \
        owl-s500-labrador-base-m.dtb \
+       owl-s500-roseapplepi.dtb \
        owl-s500-sparky.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += \
        prima2-evb.dtb

diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
new file mode 100644 (file)
index 0000000..a2087e6
--- /dev/null
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Roseapple Pi
+ *
+ * Copyright (C) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "owl-s500.dtsi"
+
+/ {
+       compatible = "roseapplepi,roseapplepi", "actions,s500";
+       model = "Roseapple Pi";
+
+       aliases {
+               serial2 = &uart2;
+       };
+
+       chosen {
+               stdout-path = "serial2:115200n8";
+       };
+
+       memory@0 {
+               device_type = "memory";
+               reg = <0x0 0x80000000>; /* 2GB */
+       };
+
+       uart2_clk: uart2-clk {
+               compatible = "fixed-clock";
+               clock-frequency = <921600>;
+               #clock-cells = <0>;
+       };
+};
+
+&twd_timer {
+       status = "okay";
+};
+
+&timer {
+       clocks = <&hosc>;
+};
+
+&uart2 {
+       status = "okay";
+       clocks = <&uart2_clk>;
+};